Semiconductor Glossary

Basic terms that come up often when studying semiconductors, organized by topic. Type a keyword to filter.

Fundamentals

Semiconductor physicsPractice questions →

Acceptor: An impurity that accepts electrons from a semiconductor and creates holes. For silicon, group III elements such as boron (B) act as acceptors and make p-type semiconductors.
Auger recombination: Recombination in which the released energy is given to another carrier instead of being emitted as light. It becomes significant at high carrier densities and affects lifetime in heavily doped layers and efficiency loss in LEDs.
Band gap: The energy difference between the top of the valence band and the bottom of the conduction band. About 1.12 eV for silicon at room temperature. A larger band gap means better tolerance to high temperatures and voltages.
Degenerate semiconductor: A semiconductor doped so heavily that the Fermi level lies inside the conduction or valence band. It behaves almost like a metal and is used in tunnel diodes and low-resistance contacts.
Diffusion length: The average distance minority carriers diffuse before recombining, given by L = √(Dτ) from the diffusion coefficient D and lifetime τ. It strongly affects the efficiency of solar cells and photodetectors.
Donor: An impurity that supplies electrons to a semiconductor. For silicon, group V elements such as phosphorus (P) and arsenic (As) act as donors and make n-type semiconductors.
Effective mass: An apparent mass used to treat electrons and holes in a crystal as if they were free particles responding to external forces. It is set by the curvature of the band; a smaller effective mass tends to give higher mobility.
Einstein relation: The relation D = μkT/q that links the diffusion coefficient D and mobility μ of carriers. It shows that materials with higher mobility also allow faster diffusion.
Electron affinity: The energy difference between the vacuum level and the bottom of the conduction band of a semiconductor. It is used to estimate band offsets at heterojunctions and barrier heights at metal contacts.
Fermi level: The energy at which the probability of an electron occupying a state is exactly one half. It lies closer to the conduction band in n-type material and closer to the valence band in p-type.
Indirect band gap: A band structure in which the bottom of the conduction band and the top of the valence band occur at different momenta. Transitions need a phonon, so light emission is inefficient. Silicon and germanium are typical examples.
Intrinsic carrier density: The density of thermally generated electrons and holes in an undoped semiconductor, written ni. For silicon it is about 1×10¹⁰ cm⁻³ at room temperature and rises steeply with temperature. In equilibrium, n × p = ni².
Mobility: How easily carriers move when an electric field is applied. In silicon, electron mobility is higher than hole mobility.
Quasi-Fermi level: Separate Fermi levels for electrons and holes, used to describe a semiconductor driven out of equilibrium by light or current injection. The larger the split between them, the more excess carriers there are.
SRH recombination (Shockley-Read-Hall recombination): Recombination of electrons and holes through deep levels (traps) in the band gap. It mainly determines minority-carrier lifetime in silicon and is accelerated by metal contamination and crystal defects.
Work function: The energy difference between the vacuum level and the Fermi level: the minimum energy needed to remove an electron from a material. It affects the threshold voltage of metal gates and the height of Schottky barriers.

PN junctions and diodesPractice questions →

Avalanche breakdown: A phenomenon in which carriers accelerated by a strong reverse field strike atoms and create new carriers, which multiply in a chain reaction so that a large current flows.
Built-in potential: The potential difference across the depletion layer of a PN junction even with no external voltage applied. About 0.6 to 0.8 V in silicon, it forms the barrier that stops further carrier diffusion.
Conductivity modulation: A large drop in the resistance of a lightly doped layer when many minority carriers are injected into it. PIN diodes and IGBTs use it to combine high breakdown voltage with low on-state voltage.
Depletion layer: A region near a PN junction boundary that contains almost no carriers. It widens under reverse bias.
Diffusion capacitance: Capacitance in a forward-biased PN junction caused by injected minority carriers stored in the neutral regions. It grows in proportion to forward current and limits high-speed operation.
Forward bias: Applying a positive voltage to the p side and a negative voltage to the n side. The barrier drops and current flows readily. The opposite is reverse bias, under which almost no current flows.
Ideality factor: The factor n in the diode equation I ∝ exp(qV/nkT). It is close to 1 when diffusion current dominates and close to 2 when recombination in the depletion layer dominates, so it indicates junction quality.
Junction capacitance (depletion capacitance): Capacitance arising because the depletion layer of a PN junction acts like a parallel-plate capacitor. It decreases as reverse bias widens the depletion layer; varactor diodes use this property.
Ohmic contact: A metal-semiconductor contact with low resistance in both directions and a linear current-voltage relation. It is made by heavily doping the semiconductor surface so carriers can tunnel through the barrier.
Reverse recovery time: The time during which reverse current keeps flowing after a conducting diode is reverse-biased, until the stored minority carriers are removed. It causes switching loss and noise.
Schottky barrier diode: A diode that uses a metal-semiconductor junction (Schottky junction). It has a low forward voltage and switches fast because there is no minority-carrier storage.
Tunnel diode (Esaki diode): A diode with very heavily doped p and n sides that shows negative resistance in forward bias due to tunneling. It was discovered by Leo Esaki in 1957.
Zener diode: A diode that provides a constant voltage by using the nearly fixed reverse breakdown voltage.

Bipolar transistorsPractice questions →

Common-emitter circuit: An amplifier circuit in which the emitter is the common terminal for input and output. It provides both current gain and voltage gain and is the most widely used configuration.
Crossover distortion: Distortion in a class-B push-pull amplifier near 0 V, where neither transistor conducts during the handover between positive and negative half-cycles. Class-AB biasing with a small idle current reduces it.
Current gain (hFE): The ratio of collector current to base current (IC/IB) in a bipolar transistor.
Current mirror: A circuit that uses two matched transistors to copy the current flowing in one into the other (or at a fixed ratio). It is widely used for bias current sources and active loads in analog ICs.
Cutoff region: The state of a bipolar transistor in which both junctions are reverse-biased and almost no collector current flows. It corresponds to a switch in the off state.
Darlington connection: A connection that feeds the emitter current of one transistor into the base of a second. The overall current gain is roughly the product of the two, so a small base current can control a large current.
Early effect: A phenomenon in which raising the collector voltage widens the base-collector depletion layer, narrowing the effective base width and slightly increasing collector current.
Emitter follower: A common-collector amplifier. Its voltage gain is about 1, but its high input impedance and low output impedance make it a buffer that drives the next stage without loading the signal.
Forward-active region: The state with the base-emitter junction forward-biased and the base-collector junction reverse-biased. A collector current proportional to the base current flows, and it is used for amplification.
HBT (heterojunction bipolar transistor): A bipolar transistor using materials with different band gaps for the emitter and base. Types include SiGe and GaAs-based devices, used in high-frequency amplifiers.
Miller effect: The effect by which a capacitance between the input and output of an inverting amplifier appears (1 + gain) times larger from the input. It degrades the high-frequency response of common-emitter and common-source stages.
Saturation region: The state of a bipolar transistor in which both the base-emitter and base-collector junctions are forward-biased. The collector-emitter voltage falls to about 0.1-0.3 V, corresponding to a switch in the on state.
Transition frequency: The frequency at which the common-emitter current gain falls to 1, written fT. It is a key indicator of a transistor's high-frequency performance.

MOSFETPractice questions →

Body effect: An increase in threshold voltage when reverse bias is applied between source and substrate (body), because the depletion charge grows. Also called the substrate bias effect; it is sometimes used to tune the threshold.
Channel-length modulation: In a saturated MOSFET, raising the drain voltage moves the pinch-off point toward the source, shortening the effective channel and slightly increasing drain current. It makes the output resistance finite.
CMOS: A circuit style that combines nMOS and pMOS transistors in a complementary way. Almost no current flows through it in steady state, so power consumption is low.
DIBL: Short for drain-induced barrier lowering. In short-channel MOSFETs, a higher drain voltage lowers the potential barrier at the source, reducing the threshold voltage and increasing off-state leakage.
Flat-band voltage: The gate voltage at which the bands at the semiconductor surface of a MOS structure are flat. It is set by the work-function difference between gate and substrate and by charges in the oxide, and is one component of the threshold voltage.
GIDL (gate-induced drain leakage): Off-state leakage caused by band-to-band tunneling in the strong field where the gate overlaps the drain. It is a concern for data retention in DRAM, among others.
Inversion layer: A layer formed at the semiconductor surface by the gate voltage, where carriers of the type opposite to the substrate gather. It becomes the MOSFET's channel.
LDD structure: Short for lightly doped drain. The drain is made lightly doped only at its edge next to the gate, relaxing the electric field and suppressing hot-carrier degradation.
Punch-through: A condition in which the source and drain depletion regions merge and current flows that the gate cannot control. It occurs when the channel is too short or the substrate doping is too low.
Short-channel effect: Phenomena in which, as gate length shrinks, the drain's electric field lowers the threshold voltage and increases off-state leakage current.
Short-circuit current: Current that flows from supply to ground in a CMOS gate during the brief time while the input switches and both the pMOS and nMOS are on. Also called crowbar current, it adds to power consumption.
Subthreshold swing: The gate voltage needed to change drain current tenfold below threshold. Its theoretical lower limit at room temperature is about 60 mV per decade; the smaller it is, the sharper the on/off switching.
Threshold voltage: The gate voltage at which a channel (inversion layer) forms in a MOSFET and current starts to flow. Written as Vth.
Transconductance: The ratio of the change in drain current to the change in gate voltage, written gm. It expresses a transistor's amplifying ability; amplifier gain is roughly gm times the load resistance.
Transmission gate: An analog switch made of an nMOS and a pMOS connected in parallel. The nMOS passes 0 well and the pMOS passes 1 well, so both values pass without voltage loss.
Velocity saturation: Under strong electric fields, carrier drift velocity stops increasing in proportion to the field and levels off at about 1×10⁷ cm/s. In short-channel MOSFETs it makes drain current smaller than the square law predicts.

Logic circuitsPractice questions →

Clock skew: The difference in arrival time of the same clock signal at different flip-flops. Because it changes setup and hold margins, clock tree synthesis keeps it small.
Combinational circuit: A logic circuit whose output depends only on its current inputs. Examples include adders, multiplexers and decoders.
De Morgan's theorem: The rules for transforming logic expressions: NOT (A AND B) equals (NOT A) OR (NOT B), and NOT (A OR B) equals (NOT A) AND (NOT B).
Decoder: A circuit that activates exactly one of 2ⁿ outputs according to an n-bit input. It is used to select the row addressed in a memory. The reverse function is an encoder.
Flip-flop: The basic element of sequential circuits that stores one bit. A D flip-flop captures its input at a clock edge.
Full adder: A circuit that adds two bits plus a carry-in from the lower digit and outputs a sum and a carry-out. A version without carry-in is a half adder. Chaining full adders makes a multi-bit adder.
Glitch: An unwanted momentary pulse on an output, caused for example by differing delays along signal paths. In combinational logic it is also called a hazard; in DACs it appears when the code changes.
Gray code: A code in which successive values differ in only one bit. It prevents read errors in rotary encoders and when passing counter values between different clock domains.
Hold time: The minimum time after the active clock edge during which a flip-flop's data input must stay unchanged. Violations are not fixed by lowering the clock frequency, so delay is added to the path.
Karnaugh map: A diagram that arranges a truth table so that adjacent cells differ in one bit. Grouping neighboring 1s lets you simplify a logic expression visually.
Metastability: A state in which a flip-flop's output stays between 0 and 1 for a while when setup or hold time is violated. Asynchronous signals are passed through two flip-flops (a synchronizer) to guard against it.
Multiplexer: A circuit that selects one of several inputs according to select signals and passes it to the output. The reverse, routing one input to one of several outputs, is a demultiplexer.
Sequential circuit: A logic circuit that stores state in flip-flops and the like, so its output depends on both inputs and past state. Examples include counters and registers.
Setup time: The minimum time before the active clock edge during which a flip-flop's data input must be stable. Paths that cannot meet it limit the maximum operating frequency.
Shift register: A chain of flip-flops that moves data one bit to the next stage on each clock. It is used for serial-parallel conversion and as the scan chain in scan testing.
Tri-state buffer: A buffer that can output 0, 1 or a disconnected high-impedance state. It prevents output conflicts when several circuits share one bus.
Truth table: A table listing the output for every combination of inputs. It is used to describe the behavior of logic circuits.
Two's complement: The usual binary representation of negative integers. Inverting all bits and adding 1 negates a number. n bits cover −2ⁿ⁻¹ to 2ⁿ⁻¹ − 1, and the same adder can be used for subtraction.

Analog and electronic circuitsPractice questions →

1/f noise (flicker noise): Noise that grows larger at lower frequencies. In MOSFETs it comes from traps at the gate-oxide interface capturing and releasing carriers, and it matters in low-frequency analog circuits.
Bandgap voltage reference: A circuit that adds a diode voltage that falls with temperature to a voltage that rises with temperature, producing a reference of about 1.2 V that barely depends on temperature. It is widely used in ADCs and power ICs.
CMRR (common-mode rejection ratio): The ratio of differential gain to common-mode gain in a differential amplifier. The larger it is, the better the circuit rejects noise that appears equally on both inputs.
Comparator: A circuit that compares two input voltages and outputs the result as a binary high or low. It is also a basic building block of AD converters.
Cutoff frequency: The frequency at which the output of a filter or amplifier falls 3 dB (to about 0.707 times) below the passband. For an RC circuit it is 1/(2πRC).
Differential amplifier: A circuit that amplifies the difference between two inputs while rejecting components common to both, such as noise. It is used as the input stage of op-amps.
Gain-bandwidth product (GBW): The product of an op-amp's gain and bandwidth, which stays roughly constant. With a GBW of 1 MHz, for example, a gain-of-10 circuit has a bandwidth of about 100 kHz.
Instrumentation amplifier: A differential amplifier, typically built from three op-amps, with high input impedance and high CMRR. It amplifies small differential signals from sensors with high accuracy.
LDO: Short for low-dropout regulator: a linear regulator that works with only a small difference between input and output voltage. It is low-noise, but the voltage difference times the current is lost as heat.
Negative feedback: Returning part of the output to the input with opposite polarity. Gain drops, but it becomes stable, and distortion and bandwidth improve.
Operational amplifier (op-amp): An amplifier with differential inputs and very high gain. Used with negative feedback in amplifiers, filters and more.
Phase margin: How far the phase lag is from 180° at the frequency where the feedback loop gain is 1 (0 dB). A small margin causes ringing, and zero or negative margin causes oscillation; 45-60° or more is a common target.
PLL (phase-locked loop): A circuit that detects the phase difference from a reference clock and controls an oscillator to produce a clock locked to the reference, for example at an integer multiple of its frequency. It is used to generate CPU clocks and synthesize radio frequencies.
PSRR (power supply rejection ratio): A measure of how little supply-voltage variation reaches a circuit's output. The larger it is, the more immune the circuit is to supply noise.
Schmitt trigger: A circuit whose switching threshold differs for rising and falling inputs (hysteresis). Its output does not chatter even with slowly changing or noisy signals.
Slew rate: The maximum rate at which an op-amp's output voltage can change, expressed in V/µs. If it is insufficient for large, high-frequency signals, the waveform distorts.
Thermal noise (Johnson noise): Noise caused by the thermal motion of electrons in a resistor. Its mean-square voltage is 4kTRΔf, proportional to temperature, resistance and bandwidth.
Time constant: A quantity describing how fast a circuit such as an RC network responds to a step; for an RC circuit τ = RC. The response reaches about 63% of its final value after τ and has nearly settled after about 5τ.
Transimpedance amplifier: An amplifier that converts an input current to a voltage. The current enters the op-amp's inverting input and a feedback resistor turns it into a voltage. It is used to read photodiode signals.
Virtual short: The property of an ideal op-amp with negative feedback that its two input voltages become nearly equal. Although no current flows between them, they can be treated as shorted, which makes gain calculations simple.
Voltage follower: A unity-gain op-amp circuit with the output tied directly to the inverting input. With high input impedance and low output impedance, it is used as a buffer.

AD/DA conversionPractice questions →

Aliasing: A phenomenon in which components above half the sampling frequency falsely appear as lower-frequency components. It is prevented with a low-pass filter before A/D conversion.
Delta-sigma ADC: An ADC that oversamples at a high rate, pushes quantization noise to high frequencies and then filters it out. Used in high-resolution applications such as audio and measurement.
DNL (differential nonlinearity): The error in each code step width of an ADC relative to the ideal 1 LSB. When it reaches −1 LSB, a missing code occurs.
ENOB (effective number of bits): The real performance of an ADC, including noise and distortion (SINAD), expressed as the bit count of an ideal ADC. A 12-bit ADC with an ENOB of around 10 bits is not unusual.
Flash ADC: The fastest type of ADC, which compares the input against many comparators at once. N bits need 2ᴺ − 1 comparators, so the circuit grows rapidly with resolution.
INL (integral nonlinearity): The maximum deviation of an ADC's or DAC's actual transfer characteristic from the ideal straight line. It corresponds to the accumulated DNL.
Jitter: Small fluctuations in the timing of clock or signal edges from their ideal positions. When sampling high-frequency signals, even slight jitter causes large voltage errors.
Missing code: A defect in which an ADC never outputs a particular code no matter how the input varies. It occurs when DNL reaches −1 LSB.
Noise shaping: A technique that uses a feedback loop to push quantization noise toward high frequencies, lowering noise in the signal band. Delta-sigma ADCs combine it with oversampling to achieve high resolution.
Nyquist frequency: Half the sampling frequency. Components above it are folded back to lower frequencies when sampled (aliasing).
Oversampling: Sampling at a rate well above what the signal requires (twice its bandwidth). It spreads quantization noise over a wider band and reduces noise in the signal band; it is the basis of delta-sigma ADCs.
Pipelined ADC: An ADC that splits conversion into stages, each resolving a few bits and passing the residue to the next, like an assembly line. It combines high speed with medium to high resolution.
Quantization error: The error that arises when rounding a continuous analog value to a digital value with a finite number of bits. At most half of one LSB.
R-2R ladder DAC: A DAC built from a ladder of only two resistor values, R and 2R. It needs few resistor types, and the resistor ratio does not grow as bits are added.
Sample-and-hold circuit: A circuit that captures (samples) the input voltage at an instant and holds it constant until AD conversion finishes. It is built from a switch and a capacitor.
Sampling theorem: The theorem stating that a signal can be reconstructed if it is sampled at a frequency higher than twice its highest frequency component. Also called the Nyquist-Shannon theorem.
Successive-approximation ADC: An ADC that uses an internal DAC and comparator to determine one bit at a time, starting from the most significant. It balances speed, accuracy and power well.

Devices

DRAMPractice questions →

1T1C cell: The DRAM memory cell that stores one bit with one transistor and one capacitor. The presence or absence of charge on the capacitor represents 0 or 1.
Bank: One of several independently operating sections inside a DRAM. Overlapping activation and access across different banks raises effective performance.
Bit line: The wire used to read and write data in memory cells. In DRAM, the small change in bit-line potential caused by a cell's charge is amplified by a sense amplifier.
CAS latency: The number of clock cycles in DRAM from a read command (specifying the column address) until data appears at the output, abbreviated CL. Smaller values mean a faster response.
DDR SDRAM: Synchronous DRAM that transfers data on both the rising and falling clock edges. Successive generations such as DDR4 and DDR5 have raised the data rate. It is the standard main memory of PCs and servers.
DIMM: A memory module that mounts several DRAM chips on a small board so it can be plugged into a slot in a PC or server.
ECC (error-correcting code): A scheme that adds redundant bits to data so that bit errors can be detected and corrected on readout. It is used in server memory, flash memory and inside DDR5 chips, among others.
LPDDR: Short for low-power DDR: a DRAM standard for smartphones and laptops with lower supply voltages and enhanced power-saving features.
Memory wall: The problem that memory bandwidth and latency improve more slowly than processor performance, limiting overall performance. HBM, larger caches and advanced packaging are used to address it.
Precharge: Charging the bit lines to a set potential (half the supply voltage in DRAM, for example) before a read. In DRAM it also means closing the open row to prepare for activating the next one.
Redundancy repair: Replacing rows or columns that contain defective memory cells with spare rows or columns prepared in advance. The defect locations are found by testing and the switch is made with fuses or similar. It greatly improves yield.
Refresh: The periodic reading and rewriting of DRAM data before the charge in its capacitors is lost through leakage.
Rowhammer: A DRAM phenomenon in which repeatedly activating the same row in a short time drains charge from cells in neighboring rows and flips their data. Because it can be exploited in attacks, countermeasures are built into DRAMs and memory controllers.
Sense amplifier: A circuit that amplifies the tiny voltage difference read from a memory cell and decides whether it is 0 or 1.
Word line: The wire connected to the gates of memory-cell transistors that selects the row to read or write.

SRAM and flash memoryPractice questions →

3D NAND: NAND flash in which memory cells are stacked vertically in many layers to increase capacity. It was introduced to get past the limits of planar scaling, and layer counts now exceed 200.
6T SRAM cell: The SRAM memory cell made of two cross-coupled inverters (four transistors) and two access transistors.
Charge-trap cell: A flash memory cell that stores electrons in traps within an insulating film such as silicon nitride instead of in a floating gate. It is mainly used in 3D NAND.
Floating gate: An electrode in a flash memory cell that is completely surrounded by insulator. Storing electrons on it shifts the transistor's threshold voltage, so data is kept even without power.
Fowler-Nordheim tunneling: Current that flows when a strong electric field lets electrons tunnel through the triangular barrier of a thin insulator. It is used to program and erase NAND flash.
Garbage collection: In an SSD, moving the still-valid data out of blocks that contain invalid data and then erasing those blocks to create free space.
NAND flash memory: Non-volatile memory in which memory cells are connected in series. It is dense and easy to scale to large capacities, and is used in SSDs and memory cards.
Nonvolatile memory: Memory that retains stored data when power is removed, such as flash memory and MRAM. DRAM and SRAM are volatile.
NOR flash memory: Flash memory with cells connected in parallel. Random reads are fast, and it is used to store programs for microcontrollers and the like.
NVMe: An interface standard for fast access to SSDs connected over PCI Express. It processes many commands in parallel and has lower latency than SATA, which was designed for HDDs.
Read disturb: In NAND flash, the gradual shift in threshold voltage of unread cells caused by the weak voltage applied to them when the same block is read many times.
SLC (single-level cell): A flash format that stores one bit per cell. With only two threshold-voltage states it is faster and more durable than multi-level formats.
TLC (triple-level cell): A flash format that stores three bits per cell, distinguishing eight threshold-voltage states. It lowers cost per bit but reduces endurance. Four bits per cell is QLC.
TRIM: A command by which the operating system tells an SSD which areas belong to deleted files. Knowing which data is no longer needed makes garbage collection more efficient.
Wear leveling: A technique that spreads writes so rewrites do not concentrate on particular flash blocks, extending the memory's life.
Write amplification: The amount of data actually written to flash exceeding what the host wrote, because of garbage collection and similar operations. The larger it is, the shorter the SSD's life.

Emerging memoriesPractice questions →

3D XPoint: Cross-point non-volatile memory jointly developed by Intel and Micron. It stacked phase-change material with OTS selectors and was sold as Optane, but the business was wound down in 2022.
Chalcogenide: A compound containing group 16 elements such as sulfur, selenium or tellurium. It is used as the recording material of phase-change memory (such as GST) and in selectors (OTS) that switch on abruptly above a threshold voltage.
Cross-point memory: Memory with a storage element at each intersection of row and column lines. It is very dense, but a selector is placed in series with each element to stop current sneaking through unselected cells.
Electroforming: An initialization step for ReRAM in which a relatively high voltage is first applied after fabrication to create the conductive filament that later switches resistance.
FeFET (ferroelectric FET): A transistor with a ferroelectric gate insulator. Its threshold voltage depends on the polarization direction, so a single transistor can store data non-volatilely and be read non-destructively.
FeRAM (ferroelectric RAM): Nonvolatile memory that stores information in the polarization direction of a ferroelectric. Writes are fast and low-power, and it is used in IC cards and the like.
In-memory computing: Performing computations such as multiply-accumulate inside the memory array to cut data movement between memory and processor. Research is under way on using resistive elements and the like for AI inference.
Magnetic tunnel junction (MTJ): A structure with a thin insulating film between two magnetic layers. Resistance is low when the layers' magnetizations are parallel and high when antiparallel. It is the storage element of MRAM.
MRAM: Non-volatile memory that stores data as the difference in resistance caused by the magnetization direction of a magnetic tunnel junction (MTJ).
PCM (phase-change memory): Nonvolatile memory that stores information by the difference between the crystalline (low-resistance) and amorphous (high-resistance) states of a chalcogenide material.
ReRAM (resistive RAM): Nonvolatile memory that applies voltage to form and break conductive paths in an oxide or similar material, storing information as differences in resistance.
SOT-MRAM: MRAM that flips magnetization by spin-orbit torque from a current in a heavy-metal layer. The write and read current paths are separate, giving fast, durable writes.
Storage-class memory: Non-volatile memory intended to bridge the gap in speed, capacity and cost between DRAM and NAND flash. Products based on 3D XPoint were the best-known example.
STT-MRAM: MRAM that writes by flipping the magnetization of the MTJ's free layer using the spin-transfer torque of a spin-polarized current. It is in volume production as embedded non-volatile memory.
TMR ratio: In an MTJ, the difference between the resistances in the parallel and antiparallel states divided by the parallel-state resistance. The larger it is, the easier it is to tell 0 from 1; MgO barriers give large values.

CPUs and architecturePractice questions →

Amdahl's law: The law that when only part of a program is parallelized, overall speedup is limited by the part that cannot be. For example, parallelizing 90% gives at most a 10x speedup.
Branch prediction: A technique that predicts the outcome of conditional branches before they execute, so later instructions can proceed without stalling the pipeline. A misprediction forces the work to be redone.
Cache coherency: In a multicore CPU, the mechanism that keeps copies of the same address in different cores' caches consistent, for example by invalidating other copies when one core writes.
Cache memory: Fast, small memory placed close to the CPU. It holds frequently used data to bridge the speed gap with main memory. Mostly built from SRAM.
DMA (direct memory access): A mechanism that transfers data directly between peripherals and memory without going through the CPU, so the CPU can do other work during large transfers.
DVFS (dynamic voltage and frequency scaling): Changing operating frequency and supply voltage dynamically according to load. Since dynamic power scales with the square of voltage, lowering voltage during light loads saves a lot of power.
GPU: Short for graphics processing unit: a processor with many simple execution units that processes large amounts of data in parallel. Besides graphics, it is widely used for AI training and inference.
Instruction set architecture (ISA): The processor specification as seen by software, including the instructions and registers it supports. Examples include x86, Arm and RISC-V.
Interrupt: A CPU mechanism that temporarily suspends the current task to handle a request, for example from an external device, and then returns to the original task.
IPC: Short for instructions per cycle: the number of instructions executed per clock. It expresses design efficiency; performance is roughly IPC times clock frequency. Its reciprocal is CPI.
Microcontroller: A small computer that integrates a CPU, memory and peripherals such as timers and ADCs on one chip. It is embedded in appliances, cars and other equipment to control them. Also called an MCU.
NPU (neural processing unit): A dedicated circuit for running neural-network inference quickly and at low power. It is built into the SoCs of smartphones and PCs.
Out-of-order execution: Executing instructions as soon as their dependencies allow, in a different order from the program, to improve performance. Results are committed in program order through a reorder buffer.
Pipelining: A method that splits instruction processing into stages such as fetch, decode and execute, and processes several instructions at once, each offset by a stage.
SIMD: Short for single instruction, multiple data: one instruction performs the same operation on several data elements at once. It speeds up image processing and AI calculations.
SMT (simultaneous multithreading): A technique in which one CPU core processes instructions from several threads at once, making better use of its execution units. Intel calls it Hyper-Threading.
Superscalar: A processor design that issues and executes several instructions per clock cycle. It has multiple execution units and processes independent instructions in parallel.
Systolic array: An arrangement of many multiply-accumulate units in a grid that computes matrix products by passing data to neighboring units step by step. It is used in AI accelerators.
TDP (thermal design power): A guide to the heat a CPU or similar chip generates under a typical heavy load. Cooling systems are designed around it.
TLB (translation lookaside buffer): A small cache that holds recent virtual-to-physical address translations. It avoids walking the page tables in memory on every access, speeding up address translation.
Virtual memory: A system in which the OS and hardware map the addresses a program uses (virtual addresses) to physical memory addresses. Each program gets a large, independent address space.
Von Neumann architecture: A computer organization that keeps programs and data in the same main memory and fetches and executes instructions in sequence.

Power semiconductorsPractice questions →

Body diode: A parasitic diode formed between source and drain by the structure of a power MOSFET. It can serve as the freewheeling diode in an inverter, but its reverse recovery needs attention.
DC-DC converter: A circuit that converts one DC voltage into another. Using switches, inductors and capacitors, buck types lower the voltage and boost types raise it.
Dead time: A short interval during which both the upper and lower switches of an inverter are off while switching between them. It prevents both from being on at once and shorting the supply.
Gate driver: A circuit that receives control signals and drives a power device's gate with the right voltage and enough current. Many include isolation or level shifting to drive high-side switches.
IGBT: Insulated-gate bipolar transistor. Driven by a MOS gate, it achieves a low on-state voltage even at high voltage ratings through conductivity modulation.
Normally-off: The property of passing no current when the gate voltage is 0 V. It is required of power devices for safety, since current stops even if the drive circuit fails.
On-resistance: The resistance of the current path when a power device is on. The smaller it is, the lower the conduction loss.
Power MOSFET: A MOSFET built to handle large currents and voltages. It switches quickly and is widely used in power supply circuits and the like.
Short-circuit withstand time: The time a power device can survive a short circuit, such as both inverter switches turning on at once, without being destroyed. Protection circuits must cut the current within this time.
SiC (silicon carbide): A wide-band-gap semiconductor with a band gap of about 3.3 eV. Its high breakdown field makes it suitable for high-voltage, low-loss power devices.
Snubber circuit: A network such as a resistor and capacitor placed across a power device to suppress the voltage spikes (surges) and ringing that occur during switching.
Soft switching: Turning a switch on or off when the voltage across it or current through it is nearly zero, as in zero-voltage switching (ZVS). It reduces switching loss and noise.
Super-junction MOSFET: A power MOSFET whose drift layer has alternating p-type and n-type pillars. It allows higher drift-layer doping without losing breakdown voltage, achieving on-resistance below the conventional silicon limit.
Switching loss: Loss that occurs while a power device switches between on and off, when voltage and current are present at the same time. It grows with switching frequency.
Tail current: Current that keeps flowing like a tail as an IGBT turns off, because stored minority carriers prevent it from dropping to zero immediately. It causes turn-off loss.

Image sensors and optical devicesPractice questions →

Backside illumination (BSI): An image sensor structure in which light enters from the back of the substrate, where there is no wiring. Light is not blocked by wiring, so sensitivity stays high even with small pixels.
Bayer pattern: A color filter arrangement of red, green, green and blue over each 2×2 block of pixels, with two greens because the eye is most sensitive to green. Missing colors at each pixel are interpolated from neighbors (demosaicing).
CCD image sensor: An image sensor that shifts pixel charges along like a bucket brigade and converts them to voltage at an output stage. It offered low noise and high image quality but used more power, and CMOS sensors have replaced it in most uses.
CMOS image sensor: An image sensor made with a CMOS process that has an amplifier in each pixel. It is low-power, can integrate peripheral circuits, and dominates smartphone cameras and more.
Correlated double sampling (CDS): Taking the difference between a pixel's voltage just after reset and its voltage when the signal is read. It removes reset noise and per-pixel offsets.
Dark current: Current that flows in a photodiode even without light, caused for example by thermal generation of carriers. It rises with temperature and appears as noise in dark images.
Fixed-pattern noise: Noise that appears in the same place every time, caused by variations between pixels or readout circuits. It is removed by correlated double sampling or calibration.
Full-well capacity: The maximum number of electrons one image-sensor pixel can hold. The larger it is, the brighter the scene can be before highlights clip, widening dynamic range.
Global shutter: An electronic shutter method that exposes all pixels at the same time. Unlike a rolling shutter, which reads row by row, it does not distort images of moving objects.
Microlens: A tiny lens placed over each pixel of an image sensor. It gathers light and directs it efficiently onto the photodiode, raising sensitivity.
Photodiode: A diode that generates charge (current) when it receives light. Used as the light-receiving element in image sensor pixels.
Pinned photodiode: A photodiode with a heavily doped p+ layer at the surface that keeps the collection region away from the interface. It suppresses dark current from interface states and allows complete charge transfer; it is standard in CMOS image sensors.
Quantum efficiency: The fraction of incident photons converted into signal electrons. The higher it is, the better the sensitivity.
Rolling shutter: A readout method that exposes and reads pixel rows one after another. It is simple, but fast-moving subjects appear skewed. Exposing all pixels at once is a global shutter.
Shot noise: Noise from statistical fluctuation in the number of photons or electrons. Its size is proportional to √N for a signal of N electrons, so it is relatively larger when light is scarce.
SPAD (single-photon avalanche diode): A photodetector biased above breakdown so that even a single photon triggers a large avalanche pulse. It is used for ranging, such as in LiDAR.
Stacked CMOS image sensor: An image sensor whose pixel array and signal-processing circuitry are made on separate chips and bonded together. Each can use the most suitable process, making the chip smaller and processing faster.
ToF (time of flight): Measuring distance from the time light takes to travel to an object and back. ToF sensors are used in face recognition, robotics and automotive LiDAR.

Compound semiconductorsPractice questions →

2DEG (two-dimensional electron gas): A dense sheet of electrons confined at a heterojunction interface such as AlGaN/GaN. With little impurity scattering and high mobility, it serves as the channel of a HEMT.
Alloy semiconductor: A semiconductor crystal that mixes several elements, such as AlGaAs or InGaN. Changing the composition tunes the band gap and lattice constant continuously.
Direct band gap: A band structure in which the bottom of the conduction band and the top of the valence band are at the same wave number. Electron-hole recombination emits light efficiently. Example: GaAs.
Efficiency droop: The drop in luminous efficiency of InGaN LEDs as current increases. Auger recombination is thought to be one cause.
Ga2O3 (gallium oxide): An oxide semiconductor with a band gap of about 4.5-4.9 eV, even wider than SiC or GaN. Its crystals can be grown from the melt, and it is being researched as a next-generation power semiconductor material.
GaAs (gallium arsenide): A III-V compound semiconductor of gallium and arsenic with a direct band gap of about 1.42 eV. Its high electron mobility makes it useful for high-frequency transistors and infrared LEDs and lasers.
GaN (gallium nitride): A III-V compound semiconductor with a band gap of about 3.4 eV. Used in blue LEDs and in high-frequency and power devices.
HEMT (high-electron-mobility transistor): A transistor that uses the high-mobility two-dimensional electron gas formed at a heterojunction interface as its channel. It is used in high-frequency and high-power applications.
III-V compound semiconductor: Semiconductors made of group III elements (Ga, In, Al, etc.) and group V elements (As, P, N, etc.), such as GaAs, InP and GaN.
InP (indium phosphide): A compound semiconductor of indium and phosphorus. As a substrate for lattice-matched layers such as InGaAs, it is used for fiber-optic lasers and photodetectors and for high-speed transistors.
MMIC: Short for monolithic microwave integrated circuit: a high-frequency IC that integrates transistors together with passive components such as inductors and capacitors on a substrate such as GaAs.
Quantum well: A structure in which a thin layer, a few nanometers thick, with a small band gap is sandwiched between layers with a larger band gap. It confines carriers to promote recombination and is used as the active layer of LEDs and lasers.
VCSEL (vertical-cavity surface-emitting laser): A semiconductor laser that emits light perpendicular to the substrate. It can be tested on the wafer and easily arranged in 2D arrays, so it is used in data links and as the light source for face recognition.
Vegard's law: The empirical rule that the lattice constant of an alloy varies almost linearly with composition. It is used to find the composition that lattice-matches a given substrate.
Wide-bandgap semiconductor: Semiconductors with a larger band gap than silicon, such as SiC and GaN. Their high breakdown field makes them strong for high-voltage, high-temperature operation.
Wurtzite structure: The hexagonal crystal structure of GaN, ZnO and others. It has polarization along certain crystal directions, which creates the 2DEG in GaN HEMTs.

Advanced transistors (FinFET and GAA)Practice questions →

CFET (complementary FET): A structure that stacks nMOS and pMOS transistors vertically. It is under development because it could greatly shrink the area of CMOS circuits.
DTCO (design-technology co-optimization): Optimizing cell area and performance by considering circuit design and process technology together, as scaling becomes harder.
EOT (equivalent oxide thickness): The thickness of SiO2 that would give the same gate capacitance as a gate insulator such as a high-k film. A physically thick film can have a small EOT, giving high capacitance while limiting tunneling current.
FD-SOI (fully depleted SOI): Building transistors in a very thin silicon layer on buried oxide so the channel is fully depleted. The channel can be lightly doped, and body bias can tune the threshold voltage easily.
FinFET: A 3D transistor whose channel stands up like a fin and is surrounded by the gate on three sides. It suppresses short-channel effects well.
GAA (gate-all-around): A transistor structure in which the gate surrounds the channel on all sides. It controls current better than FinFET and is used in the generations after FinFET.
Gate-last (replacement metal gate): Building the transistor first with a dummy gate, then removing it after high-temperature steps such as source/drain activation and replacing it with a high-k dielectric and metal gate.
High-k / metal gate: The combination of a high-dielectric-constant gate insulator and a metal gate electrode. It keeps gate capacitance high while suppressing gate leakage.
Nanosheet: A GAA transistor structure that stacks several thin, plate-like silicon channels vertically, each surrounded by the gate. Current can be tuned by the sheet width.
Random dopant fluctuation (RDF): Threshold-voltage variation in small transistors caused by statistical variation in the number and position of dopant atoms in the channel. FinFETs and FD-SOI, which allow lightly doped channels, reduce it.
SADP (self-aligned double patterning): Forming spacers on the sidewalls of a core pattern, removing the core and using the spacers as the mask to make a pitch half of what lithography alone allows. Doing it twice is SAQP.

MEMS and sensorsPractice questions →

Accelerometer: A sensor that detects acceleration from the movement of a small spring-supported mass. It is used for detecting smartphone orientation, in airbags and elsewhere.
Anodic bonding: Joining silicon to sodium-containing glass by heating them together while applying a voltage. It is used, for example, to seal MEMS devices.
Bosch process (deep RIE): A dry-etching technique that alternates short etch and sidewall-passivation steps to cut deep, vertical holes and trenches in silicon. It is used for MEMS and TSVs.
Capacitive sensing: A method that detects displacement, pressure and the like from changes in capacitance between movable and fixed electrodes. It is widely used in MEMS sensors.
Coriolis force: An apparent force acting perpendicular to the motion of an object moving in a rotating frame. Vibratory MEMS gyroscopes detect angular rate from the displacement it causes.
Gyroscope: A sensor that detects rotation rate (angular velocity). MEMS versions use the Coriolis force acting on a vibrating structure.
Hall-effect sensor: A sensor that detects magnetic fields using the Hall effect: a magnetic field applied to a current-carrying semiconductor produces a voltage perpendicular to both. It is used, for example, to sense motor rotation.
MEMS: Micro-electro-mechanical systems. Devices that integrate tiny mechanical structures and electronic circuits using semiconductor microfabrication.
Piezoresistive effect: The change in a material's electrical resistivity under mechanical stress. It is especially large in silicon and is used in semiconductor pressure sensors and similar devices.
Sacrificial layer etching: A typical MEMS fabrication method that etches away a temporary layer (the sacrificial layer) beneath a structure, freeing beams or membranes so they can move.
Stiction: The sticking of tiny moving MEMS parts to the substrate through surface tension or surface adhesion, so they no longer move. It often happens during drying after sacrificial-layer removal.

Front-end processes

Silicon wafersPractice questions →

Crystal orientation: The direction of crystal planes and axes, expressed with Miller indices such as (100). The (100) surface is standard for silicon wafers used for MOSFETs.
Czochralski (CZ) method: A method of making single-crystal silicon by dipping a seed crystal into molten silicon in a crucible and slowly pulling it up while rotating.
DZ (denuded zone): A layer near the wafer surface with few defects such as oxygen precipitates, made by out-diffusing oxygen during heat treatment. Devices are built in this layer while precipitates deeper inside provide gettering.
FZ method (float zone): A method that melts a zone of a polysilicon rod and moves that molten zone along to form a single crystal. With no crucible, oxygen content is low, suiting high-resistivity wafers.
Gettering: A technique that collects and traps metal impurities in a wafer at locations away from the surface where devices are built, using oxygen precipitates and the like.
Ingot: A cylindrical single-crystal block grown by the CZ method or similar, before it is cut into wafers. The ends are removed and the outside is ground to a uniform diameter before slicing.
MCZ method (magnetic-field-applied CZ): A CZ variant that applies a magnetic field to the crucible to suppress melt convection. It makes the oxygen concentration in the crystal easier to control and is used for large-diameter crystals.
Monitor wafer: A wafer run through a process separately from products to check equipment or measure film thickness and particles. Also called a test wafer, it is often stripped, repolished and reused as a reclaimed wafer.
Necking: Growing a thin neck just after the seed at the start of CZ pulling. It lets dislocations created by thermal shock when the seed touches the melt escape, giving a dislocation-free crystal.
Notch: A small cut in a wafer's edge that indicates its crystal orientation. Used on 200 mm and larger wafers; smaller wafers used an orientation flat (a straight edge) instead.
Oxygen precipitates (BMD): Tiny defects formed inside a CZ silicon wafer when its oxygen precipitates during heat treatment. Also called BMDs (bulk micro defects), they serve as gettering sites that capture metal impurities.
Segregation coefficient: The ratio of impurity concentration in the crystal to that in the melt during solidification. For most impurities it is below 1, so they concentrate in the melt and the later part of a CZ crystal has higher impurity levels.
Siemens process: A method that reduces trichlorosilane with hydrogen to deposit high-purity polycrystalline silicon on heated silicon rods. It is the main way to make raw silicon for semiconductors.
Slip: A defect in which crystal planes shift and dislocations form under stress from temperature differences or the wafer's own weight during high-temperature processing of large wafers. It can cause problems such as overlay errors.
SOI wafer: A wafer with a thin silicon layer on a buried oxide (BOX) layer over a silicon substrate. It is made, for example, by bonding a hydrogen-implanted wafer and splitting it. Its low parasitic capacitance suits FD-SOI devices and MEMS.
Thermal donor: Oxygen clusters that act as donors when CZ silicon is heated around 450°C. Because they change the wafer's resistivity, they are annihilated by a higher-temperature treatment.

Epitaxial growthPractice questions →

4H-SiC: The SiC polytype mainly used for power devices. It has a wide band gap of about 3.3 eV and relatively high electron mobility.
Autodoping: Unintended incorporation into a growing epitaxial layer of dopant from the substrate or elsewhere via the gas phase. It is a problem when growing lightly doped layers on heavily doped substrates.
Critical thickness: The maximum thickness to which a lattice-mismatched layer can be grown while staying strained without forming dislocations. Beyond it, misfit dislocations appear.
Epitaxial growth: A technique for growing a single-crystal thin film on a single-crystal substrate with the same crystal orientation as the substrate.
Epitaxial lateral overgrowth (ELO): Growing crystal from mask openings and letting it spread sideways over the mask. Dislocations from below do not propagate into the overgrown regions, reducing dislocations in materials such as GaN.
Heteroepitaxy: Growing a single-crystal film of a material different from the substrate, such as SiGe on silicon or GaN on sapphire. Growth of the same material is homoepitaxy.
HVPE (hydride vapor phase epitaxy): Vapor-phase growth using gallium chloride, formed by reacting HCl with gallium, together with ammonia. Its very high growth rate is used to grow thick GaN crystals for free-standing substrates.
Lattice mismatch: A difference in the atomic spacing (lattice constant) between a grown film and its substrate. A large mismatch causes strain and defects such as dislocations.
MBE (molecular beam epitaxy): Epitaxial growth in ultra-high vacuum by supplying source materials to the substrate as molecular beams. It controls thickness and composition at the atomic-layer level and is used in compound-semiconductor research and quantum structures.
Misfit dislocation: A dislocation at the interface between crystals with different lattice constants that relieves strain. It forms when the grown layer exceeds the critical thickness.
MOCVD (metal-organic chemical vapor deposition): A method that grows crystals using metal-organic compounds and source gases such as ammonia. It is widely used to grow compound semiconductors such as GaN and GaAs.
Selective epitaxial growth: A method that grows crystal only where silicon is exposed, not on areas covered by insulating film. It is used for SiGe in transistor sources and drains and elsewhere.
SiGe (silicon-germanium): An alloy of silicon and germanium with a larger lattice constant than silicon. Grown epitaxially, it is used to strain channels, as the base of HBTs and as the sacrificial layer in GAA transistors.
Stacking fault: A planar defect in which the stacking order of atomic planes is disrupted. It is a concern in epitaxial layers, thermal oxidation (OSF) and SiC crystals.
Step-flow growth: A growth mode in which the crystal extends sideways from atomic steps on a slightly off-axis substrate. In SiC it is used so the layer inherits the substrate's polytype.
Strained silicon: Silicon whose band structure is modified by strain to raise carrier mobility. Tensile strain helps nMOS and compressive strain helps pMOS; it is applied with SiGe source/drain regions, nitride films and the like.
Superlattice: A periodic structure of alternating layers of different materials, each a few nanometers thick. It shows electronic properties absent in bulk crystals and is used in lasers, buffer layers and more.
Threading dislocation: A dislocation that runs up through the grown layer to the surface. GaN on sapphire or silicon has high densities (about 10⁸-10⁹ cm⁻²), which degrade device performance and reliability.

Oxidation and diffusionPractice questions →

Bird's beak: In LOCOS, the beak-shaped encroachment of oxide under the edge of the nitride mask. Because it wastes active area, it led to the switch to STI at finer geometries.
Deal-Grove model: A model of thermal oxidation in which the oxidant diffuses through the oxide and reacts with silicon at the Si/SiO2 interface. Thickness grows linearly with time for thin oxides and with the square root of time for thick ones.
Drive-in: In thermal diffusion, the high-temperature step after a fixed amount of dopant has been introduced at the surface (predeposition), which pushes the dopant deeper.
Dry oxidation: Thermal oxidation with dry oxygen. Growth is slow, but it produces dense, high-quality oxide, used for gate oxides and the like.
Forming gas anneal: Heat treatment in a mixture of hydrogen and nitrogen (forming gas). Hydrogen terminates dangling bonds at the Si/SiO2 interface, reducing interface states.
Interface states: Energy levels within the band gap at a semiconductor-insulator interface, created by broken bonds and similar defects. They trap and release carriers, causing threshold shifts, lower mobility and noise.
LOCOS: A method that isolates devices by thickly oxidizing only areas not covered by nitride. It forms a beak-like encroachment at the edges (the bird's beak) and has been replaced by STI.
Mobile ions: Ions such as sodium and potassium that can move within the gate oxide. They drift with field and temperature and shift the threshold voltage. Because they can come from sources such as human sweat, they are tightly controlled.
Oxidation-enhanced diffusion (OED): Faster diffusion of boron and phosphorus during oxidation than without it, caused by silicon interstitials injected into the silicon by the oxidation.
Oxynitride (SiON): Gate oxide with nitrogen incorporated. It blocks boron penetration from the gate electrode and has a slightly higher permittivity, so it was used as the gate insulator before high-k films.
RTP (rapid thermal processing): Heating single wafers to high temperature for a few seconds, typically with lamps. It allows annealing and thin oxide growth while limiting unwanted dopant diffusion.
STI (shallow trench isolation): Isolating devices by etching shallow trenches in silicon, filling them with insulator and planarizing by CMP. It has no bird's beak like LOCOS and is the standard isolation for fine-pitch LSIs.
Thermal diffusion: A doping method that diffuses impurity atoms into a semiconductor at high temperature. They spread from regions of high concentration to low.
Thermal oxidation: A method of forming an SiO2 film on silicon by heating it in oxygen or water vapor. There are dry and wet oxidation.
Wet oxidation: Thermal oxidation in an atmosphere containing water vapor. It grows faster than dry oxidation and is used to make thick oxides.

Ion implantationPractice questions →

Annealing: Heat treatment. Used to repair crystal damage after ion implantation and to activate dopants, among other purposes.
Channeling: A phenomenon in which ions pass through gaps between rows of crystal atoms and penetrate deeper than expected. It is prevented by tilting the wafer during implantation and similar measures.
Faraday cup: A device that collects an ion beam and measures the resulting current. In ion implanters it is used to determine the implanted dose.
Halo implant (pocket implant): Angled implantation of dopant of the same type as the channel near the source and drain edges. It limits the spread of the drain depletion region and suppresses short-channel effects.
Implant dose: The number of ions implanted per unit area in ion implantation, expressed in cm⁻². It is set by beam current and implant time.
Ion implantation: A technique that ionizes impurities, accelerates them and implants them into the wafer. The dose and depth can be controlled precisely.
Laser anneal: Heating only the near-surface region of a wafer for an extremely short time with laser light. It achieves high activation with almost no diffusion.
Plasma doping: Implanting low-energy ions by exposing the wafer directly to a plasma containing the dopant. It delivers high doses quickly and dopes 3D structures such as fins fairly uniformly.
Pre-amorphization implant (PAI): Implanting germanium or similar first to make the surface amorphous, so that the following implant does not channel and a shallow junction results.
Projected range: The average depth at which implanted ions come to rest. It is deeper with higher acceleration energy and with lighter ions.
Retrograde well: A well whose doping is higher deeper below the surface, made by high-energy implantation. It suppresses punch-through and latch-up while keeping the channel doping at the surface low.
Shadowing: When implanting at a tilt, the effect of tall patterns such as resist casting shadows so that some areas receive no implant.
Solid solubility: The maximum concentration of an impurity that can dissolve in a crystal at a given temperature. It sets the upper limit of electrically active dopant concentration.
Spike anneal: An anneal that ramps the wafer quickly to a high temperature and cools it again with almost no hold time. It activates dopants while limiting diffusion, for shallow junctions.
Transient enhanced diffusion (TED): A temporary speed-up of boron and other dopant diffusion early in post-implant annealing, caused by excess silicon interstitials from the implant. It hinders the formation of shallow junctions.

Deposition (CVD and PVD)Practice questions →

ALD: Atomic layer deposition. A deposition method that repeats self-limiting surface reactions of precursor gases to control film thickness one atomic layer at a time.
Area-selective deposition: Growing a film only in certain places by exploiting differences in the underlying materials. Because it can save lithography and etch steps, it is being researched and introduced for advanced interconnects.
CVD: Chemical vapor deposition. A method of depositing thin films on a wafer through chemical reactions of source gases.
Electroplating: Depositing metal by passing current through a plating bath with the wafer as the cathode. It fills copper interconnect trenches, with additives making the fill proceed from the bottom up.
Electrostatic chuck: A mechanism that holds the wafer to its stage by electrostatic force. It works in vacuum and allows backside gas for temperature control; it is widely used in deposition and etch tools.
HDP-CVD (high-density plasma CVD): CVD using a high-density plasma that deposits while ion sputtering trims film at the trench openings. It has been used to fill narrow trenches with insulator without voids.
LPCVD (low-pressure CVD): Thermal CVD performed under reduced pressure. Faster gas diffusion gives good thickness uniformity and step coverage, and many wafers can be processed at once in a vertical furnace. It is used for polysilicon and nitride films.
Magnetron sputtering: Sputtering with magnets behind the target that trap electrons near it and raise plasma density. It increases deposition rate and is the mainstream sputtering method today.
PECVD (plasma-enhanced CVD): CVD that decomposes source gases with plasma to deposit films. It can deposit at lower temperatures than thermal CVD and is used for insulating films in interconnect steps and the like.
Reactive sputtering: Sputtering a metal target in an atmosphere containing a reactive gas such as nitrogen or oxygen to form nitride or oxide films. It is used for films such as titanium nitride (TiN).
Spin coating: Dispensing a liquid at the center of the wafer and spinning it at high speed so centrifugal force spreads a thin, uniform film. It is used for photoresist and spin-on dielectrics.
Sputtering: A type of PVD in which ions in a plasma bombard a target and the ejected atoms are deposited on the wafer.
Step coverage: A measure of how uniformly a film covers the sidewalls and bottoms of steps and holes compared with flat areas. ALD gives excellent step coverage.
TEOS: Short for tetraethoxysilane, a liquid organosilicon compound widely used as the source for CVD silicon oxide. It gives oxide films with good step coverage.
Vacuum evaporation: Forming a film by heating a material in vacuum until it evaporates and condenses on the substrate. Electron-beam heating handles high-melting-point materials, but step coverage is poor.

LithographyPractice questions →

ArF excimer laser: A laser using argon and fluorine that emits 193 nm ultraviolet light. Combined with immersion, ArF immersion lithography is a leading-edge technique alongside EUV. The 248 nm version is the KrF excimer laser.
Bottom anti-reflective coating (BARC): A layer coated under the resist that suppresses standing waves in the resist and dimension variation over topography caused by light reflected from the substrate.
Chemically amplified resist: A resist in which acid generated by exposure catalyzes a chain of reactions during the post-exposure bake (PEB). It needs little exposure dose and is widely used from KrF onward, but is sensitive to basic contamination.
Depth of focus (DOF): The range of focus over which a pattern prints with acceptable quality. Raising the numerical aperture improves resolution but reduces DOF, which makes wafer planarity important.
EUV lithography: Lithography using extreme ultraviolet light with a wavelength of 13.5 nm. It uses reflective optics and a vacuum environment.
High-NA EUV: Next-generation EUV lithography that raises the projection optics' numerical aperture from 0.33 to 0.55 to improve resolution.
Immersion lithography: Exposure with the space between the lens and the wafer filled with water. It allows a numerical aperture above 1, so ArF excimer lasers can form finer patterns.
Line edge roughness (LER): Nanometer-scale roughness along the edges of fine resist lines. It causes line-width variation (LWR) and leads to variation in transistor characteristics.
Multiple patterning: Forming patterns with a pitch too fine for a single exposure by splitting them across several exposures or process steps. Splitting into two is double patterning.
Nanoimprint lithography: Transferring patterns by pressing a mold with fine features into resist on the wafer. It can make fine patterns without expensive optics.
Numerical aperture (NA): A value that expresses the range of angles of light a lens can collect. A larger NA gives higher resolution.
OPC (optical proximity correction): A technique that corrects mask patterns in advance, anticipating distortion of the printed pattern caused by diffraction of light and similar effects.
Overlay: How accurately a new pattern is placed relative to the patterns made in earlier steps. Misalignment causes defects such as missed contacts, so it is controlled at the nanometer level.
Pellicle: A thin membrane stretched a short distance above a photomask. It keeps particles off the mask surface, and particles landing on the pellicle are out of focus and do not print.
Phase-shift mask: A photomask that shifts the phase of light passing through neighboring openings, using interference to improve image contrast and resolution.
Photomask (reticle): The master pattern used for exposure, typically a light-blocking pattern on a quartz substrate (reflective for EUV). For reduction scanners it is made four times larger than the pattern on the wafer.
Photoresist: A light-sensitive material whose solubility in developer changes when exposed. In positive resist the exposed areas dissolve; in negative resist they remain.
Positive photoresist: A photoresist whose exposed areas dissolve and are removed during development. One whose exposed areas remain is a negative resist.
Process window: The range of exposure dose and focus over which pattern dimensions stay within tolerance. The wider it is, the more robust manufacturing is to variation.
Scanner: An exposure tool that moves the mask and wafer in sync under a slit of light. It is the mainstream production lithography tool and generally projects the mask pattern at 1/4 size.

EtchingPractice questions →

ALE (atomic layer etching): Etching by alternating surface modification and removal so that each cycle removes about one atomic layer. It gives extremely precise control of etch depth.
Anisotropic etching: Etching that proceeds only in a particular direction (mainly vertically). Needed to pattern fine features.
Antenna effect: Damage to a gate oxide when a connected conductor, such as a long wire, collects charge like an antenna during plasma processing. Design rules limit the area ratio of such wires to prevent it.
ARDE (aspect-ratio-dependent etching): The slowdown of etch rate in narrower, deeper features because ions and radicals reach the bottom less easily. Also called the microloading effect.
Ashing: Removing photoresist that is no longer needed after etching or implantation by oxidizing it to ash, typically with an oxygen plasma.
Aspect ratio: The ratio of a hole's or trench's depth to its width. Higher ratios make etching and deposition harder; memory holes in 3D NAND reach several tens or more.
Buffered hydrofluoric acid (BHF): Hydrofluoric acid buffered with ammonium fluoride. It is used for wet etching of SiO2 with a stable etch rate and little damage to resist.
Dry etching: Removing material with plasma or gas instead of liquid chemicals. Combining ion bombardment allows anisotropic etching, which is essential for fine patterns.
Endpoint detection: Detecting the moment when the target film has been fully etched, commonly by monitoring changes in the plasma's emission spectrum.
Hard mask: A durable mask of nitride, carbon, metal or similar used when photoresist alone cannot survive the etch, for example in deep-hole etching.
ICP (inductively coupled plasma): A method that generates a high-density plasma with RF current in a coil. It makes it easy to control plasma density and the energy of ions reaching the wafer independently.
Isotropic etching: Etching that proceeds at the same rate vertically and laterally. It cuts in under the mask (undercut).
Overetch: Continuing to etch for a set time after endpoint so the film is removed everywhere on the wafer. It is done under conditions with high selectivity to the underlying layer.
Plasma: A state in which a gas is ionized into a mixture of electrons, ions and radicals (reactive neutrals). It is used in many processes, including dry etching, plasma CVD and ashing.
Radical: A neutral atom or molecule with an unpaired electron that is highly reactive chemically. Plasmas contain far more radicals than ions, and they drive chemical etching and deposition.
RIE (reactive ion etching): Dry etching that combines reactive species in a plasma with ions accelerated by an electric field. It enables vertical, anisotropic etching.
Seasoning: Running dummy wafers before product to stabilize the condition of an etch (or similar) chamber's walls, since wall changes alter process results.
Selectivity: In etching, the ratio of the etch rate of the target film to that of the mask or underlying film. Higher selectivity means less damage to the underlayer.
Self-bias: The negative DC potential that the wafer electrode naturally acquires in a capacitively coupled plasma. It accelerates positive ions toward the wafer, aiding anisotropic etching.
Wet etching: Etching that dissolves films by immersing them in chemicals. Selectivity is high and damage low, but it generally proceeds isotropically and does not suit fine patterning.

CMP and cleaningPractice questions →

Ceria (cerium oxide): An abrasive used in CMP slurries. It reacts chemically with oxide and gives high selectivity to nitride, so it is used for STI CMP.
CMP: Chemical mechanical polishing. Planarizes the wafer surface by combining the chemical action of a slurry with mechanical polishing by a pad.
Dilute hydrofluoric acid (DHF): Hydrofluoric acid diluted with water. It removes native oxide from silicon and leaves a hydrophobic, hydrogen-terminated surface.
Dishing: A CMP phenomenon in which the center of a wide metal line is over-polished into a dish-like depression.
Erosion: In CMP, excessive polishing of an entire region of dense lines, insulator included, so it ends up lower than its surroundings. Along with dishing of wide lines, it is a typical CMP defect.
Megasonic cleaning: A cleaning method that applies ultrasound of about 1 MHz to the cleaning solution to remove fine particles from wafer surfaces.
Native oxide: A thin oxide about 1 nm thick that forms naturally when silicon is exposed to air or water. Because it raises contact resistance and disturbs epitaxial growth, it is removed right before such steps.
Pad conditioning: Abrading the surface of a CMP polishing pad with a diamond tool to restore its texture and slurry-holding ability, stabilizing the removal rate. Also called dressing.
Pattern collapse: A defect in which tall, fine patterns topple or stick together during cleaning and drying because of the surface tension of liquid left between them.
Preston's equation: The empirical rule that the CMP removal rate is proportional to the product of polishing pressure and the relative speed between pad and wafer.
RCA clean: A cleaning method that removes particles and organics with SC-1 (ammonia and hydrogen peroxide) and metal contamination with SC-2 (hydrochloric acid and hydrogen peroxide).
SC-1 (APM): A mixture of ammonia, hydrogen peroxide and water used first in RCA cleaning. It removes particles and organics while lightly etching the surface.
SC-2 (HPM): A mixture of hydrochloric acid, hydrogen peroxide and water used after SC-1 in RCA cleaning to remove metal contamination.
Single-wafer cleaning: A cleaning method that processes one wafer at a time. It minimizes cross-contamination and allows per-wafer control. Immersing many wafers in a tank at once is batch cleaning.
Slurry: The liquid used in CMP, with fine abrasive particles dispersed in chemicals. It flattens surfaces by combining chemical action with mechanical polishing.
SPM (sulfuric acid-hydrogen peroxide mixture): A mixture of sulfuric acid and hydrogen peroxide. Its strong oxidizing power removes organics such as resist.

Interconnect processesPractice questions →

Air gap: Leaving part of the insulator between wires as empty space. Since air has a relative permittivity of about 1, it greatly reduces capacitance between wires.
Backside power delivery: Placing the power wiring on the back of the wafer so the front-side wiring can be used for signals. It reduces voltage drop and routing congestion.
Barrier metal: A thin metal film around copper wiring that prevents copper from diffusing into insulating films or silicon, such as Ta or TaN.
Black's equation: An empirical formula for interconnect lifetime under electromigration in terms of current density and temperature. Lifetime is inversely proportional to a power of current density and falls exponentially as temperature rises.
Crosstalk: Noise that appears on one wire when the signal on a neighboring wire changes, mainly through capacitive coupling. Wider spacing and shield wires reduce it.
Damascene process: A method of forming interconnects by etching trenches in an insulating film, filling them with metal, and removing the excess metal by CMP. Used for copper wiring.
Dual damascene: Forming both the trench for a wire and the hole for a via in the insulator, filling them with copper together and finishing with a single CMP step. It reduces process steps.
Interconnect via: A conductor that electrically connects the wiring layers above and below it in a multilevel interconnect. It is made by filling a hole in the insulator with metal.
IR drop: The drop in supply voltage reaching a circuit because current (I) flows through the resistance (R) of the power wiring. It increases delay and can cause malfunctions.
Low-k material: An interlayer dielectric with a low dielectric constant. It lowers the capacitance between wires, reducing signal delay and power consumption.
MOL (middle of line): The contacts and local interconnects that link transistors (FEOL) to the multilevel wiring (BEOL). With scaling, their resistance has grown and now limits performance.
Multilevel interconnect: A structure that stacks many wiring layers separated by insulating films and connects them vertically with vias. Leading-edge LSIs have more than ten layers.
Passivation layer: A film formed as the topmost layer of a chip to protect the circuitry from moisture, contamination and mechanical damage. Silicon nitride and polyimide are typical materials.
RC delay: Signal delay determined by the product of wire resistance (R) and capacitance (C). It grows as scaling makes wires thinner, limiting performance.
Seed layer: A thin copper film deposited by sputtering or similar before copper electroplating. It provides the conductive path for the plating current.
Silicide: A compound of silicon and a metal, such as NiSi or TiSi2. It is formed on source, drain and gate surfaces to reduce resistance and contact resistance.
Skin effect: The concentration of high-frequency current near the surface of a conductor, which raises its effective resistance. The higher the frequency, the thinner the surface layer carrying the current.
Transistor contact: The connection between a transistor's source, drain or gate and the lowest wiring layer. It is made by filling a contact hole in the insulator with tungsten or similar metal.

Process materials (gases and chemicals)Practice questions →

Arsine (AsH3): A gas compound of arsenic and hydrogen used to introduce n-type dopant (arsenic) and to grow compound semiconductors such as GaAs. It is extremely toxic.
Mass flow controller (MFC): A device in deposition and etch tools that precisely measures the mass flow of a gas and holds it at a set value.
NF3 (nitrogen trifluoride): A gas used for cleaning CVD chambers and the like. Its global warming potential is high, so emission reduction is required.
Phosphine (PH3): A gas compound of phosphorus and hydrogen used to introduce n-type dopant (phosphorus) into silicon. It is extremely toxic.
Precursor: A source compound that reacts to form the desired film in CVD or ALD, such as TEOS or metal-organic compounds.
Silane (SiH4): A gas compound of silicon and hydrogen used as the source for CVD of polysilicon, silicon oxide and silicon nitride. It ignites spontaneously in air, so it is handled under strict control.
Specialty gases: High-purity gases with toxic or flammable properties used in semiconductor manufacturing, such as silane, arsine and phosphine. They are supplied under strict control.
TMAH: Tetramethylammonium hydroxide, a metal-ion-free organic alkali used as a photoresist developer. Care is needed because it can cause poisoning through skin absorption.
Ultrapure water: Water from which ions, particles and organic matter have been removed to the extreme. Used in large amounts for wafer cleaning, with purity controlled by resistivity and other measures.

Back-end and evaluation

Packaging and assemblyPractice questions →

Backgrinding: Grinding the back of a wafer before dicing to thin it for packaging. Chips for stacking are thinned to a few tens of micrometers.
BGA: Ball grid array. A high-pin-count package with solder balls arranged in a grid on its underside.
CSP (chip-scale package): A general term for packages shrunk to nearly the size of the chip. They are widely used in compact devices such as smartphones.
Dicing: Cutting a wafer into individual chips (dies). Besides sawing with a rotating blade, there are methods such as stealth dicing, which forms a modified layer inside the wafer with a laser.
Die bonding: Attaching and fixing a diced chip at its position on a lead frame or package substrate, using adhesive, solder or sintered material.
Flip chip: A mounting method in which the chip is placed face down and connected directly to the substrate with bumps. Short connections make it suitable for high pin counts.
Lead frame: A thin metal sheet combining the pad that holds the chip with the external terminals (leads). It is used in packages such as QFP.
Reflow soldering: Printing solder paste on a circuit board, placing components and heating everything in an oven to melt the solder. It is the standard method for surface mounting.
Thermal resistance: A measure of how hard it is for heat to flow, in °C/W. Multiplying dissipated power by thermal resistance gives the temperature rise. Junction-to-ambient thermal resistance is written θJA.
Underfill: Resin filled into the gap between the chip and the substrate in flip-chip assembly. It spreads out stress from thermal expansion mismatch and protects the bump joints.
Wire bonding: A method of connecting the chip's bond pads to a lead frame or substrate with thin wires of gold, copper or similar metals.
WLP (wafer-level package): A package in which redistribution wiring and external terminals are formed while the chips are still in wafer form, before dicing. The result is a small package about the size of the chip.

Testing and inspectionPractice questions →

ATE (automatic test equipment): Equipment that applies test patterns to chips, measures their outputs and automatically judges pass or fail. Also called a tester.
ATPG (automatic test pattern generation): Automatically generating test patterns that detect faults from a circuit's netlist. It is used together with scan design.
BIST (built-in self-test): Test circuitry built into the chip so that it generates test patterns and checks results by itself. It is widely used, for example, to test memories.
Burn-in: A test that operates products under stress such as high temperature and high voltage to remove units prone to early failure before shipment.
DFT (design for testability): A design approach that builds test features such as scan chains and BIST into the circuit in advance.
Fault coverage: The fraction of modeled faults that a set of test patterns can detect. The higher it is, the less likely defective chips are to escape.
IDDQ test: A test that measures the supply current of a CMOS circuit at rest and flags defects such as bridging faults when it is abnormally high.
KGD (known good die): A chip confirmed to be good before packaging. It matters when several chips go into one package, because a single bad chip ruins the whole module.
Probe card: A fixture that presses many needles (probes) onto chip electrodes on the wafer to connect them electrically to a tester.
Scan test: A test method that uses scan chains, formed by linking a circuit's flip-flops in series, to set and observe internal states.
Stuck-at fault: The basic fault model in logic testing, which assumes a signal line is stuck at 0 or 1.
Wafer test (probe test): Checking the electrical characteristics of each chip on the wafer by touching probes to its pads before dicing. It finds bad chips before assembly so they are not packaged needlessly.

Metrology and analysisPractice questions →

AFM (atomic force microscope): A microscope that traces a sharp tip over a sample and measures fine surface topography from the forces between tip and surface. It is used, for example, to evaluate surface roughness.
CD-SEM: A scanning electron microscope for measuring pattern line widths (critical dimensions). Used for dimensional control after lithography and etching.
Defect inspection system: Equipment that finds particles and pattern defects on wafers, for example by detecting scattered light or by comparing images of neighboring dies.
EDX (energy-dispersive X-ray spectroscopy): An analysis method that measures the energies of characteristic X-rays emitted under an electron beam to identify which elements are present and how much. It is used with SEM or TEM.
Ellipsometry: A measurement method that shines polarized light on a sample and determines thin-film thickness and refractive index from the change in polarization on reflection. It is nondestructive.
FIB (focused ion beam): An instrument that mills or deposits material with a finely focused ion beam. It is used for cross-sectioning tiny areas, preparing thin TEM samples and editing circuits.
Four-point probe method: A method that passes current through the outer two of four collinear needles and measures voltage across the inner two to find the sheet resistance of wafers and thin films.
SEM (scanning electron microscope): A microscope that scans a finely focused electron beam over a sample and detects secondary electrons and other signals to image the surface. It resolves features of a few nanometers, far beyond optical microscopes.
SIMS (secondary ion mass spectrometry): A method that sputters a sample with primary ions and mass-analyzes the secondary ions to measure impurity depth profiles with high sensitivity.
TEM (transmission electron microscope): A microscope that observes thinned samples by passing an electron beam through them. With atomic-level resolution, it reveals cross-sectional structures and crystal defects.
TXRF (total reflection X-ray fluorescence): An analysis method that shines X-rays at a grazing angle so they totally reflect, then sensitively measures the fluorescent X-rays from trace metal contamination on the wafer surface.
XPS (X-ray photoelectron spectroscopy): An analysis method that determines the elements in the top few nanometers of a surface and their chemical bonding states from the energies of photoelectrons emitted under X-ray irradiation.
XRD (X-ray diffraction): An analysis method that shines X-rays on a crystal and uses the angles and intensities of the diffracted beams to determine crystal structure, lattice constant, film strain and crystal quality.

Yield and quality controlPractice questions →

APC (advanced process control): Automatically adjusting the process settings for the next lot or wafer based on earlier measurements, as in run-to-run control. It reduces variation.
Cause-and-effect diagram: A diagram that organizes the causes affecting a problem (the effect) in the shape of a fish skeleton. Also called a fishbone diagram.
Control chart: A chart that plots process measurements over time against a center line and control limits (usually ±3σ) to judge whether the process is stable. Points outside the limits or runs on one side signal problems.
FMEA (failure mode and effects analysis): A method that lists the possible failure modes of a product or process, evaluates their effects and severity, and plans countermeasures in advance.
Killer defect: A defect that makes a chip fail, such as particles or pattern anomalies of a size and location that cause shorts or opens in wiring.
Pareto chart: A chart that lists items such as defect types as bars in descending order of count, with a line for the cumulative share. It shows which items to tackle first.
Poisson yield model: A model that assumes defects are randomly distributed and expresses yield as Y = exp(−D×A), where D is defect density and A is chip area.
Process capability index (Cpk): An index of how much margin a process's variation and mean offset leave relative to the specification limits. A common benchmark is 1.33 or higher.
SPC (statistical process control): A method of maintaining quality by monitoring process data with control charts and the like and detecting anomalies statistically.
Systematic defect: A defect that occurs repeatedly at particular patterns or locations because of interactions between design and process. It is distinguished from random defects caused by chance particles.
Yield: The proportion of good products to the total produced. A key factor in semiconductor manufacturing cost.

ReliabilityPractice questions →

Arrhenius model: A model in which reaction or degradation rates vary with temperature as exp(−Ea/kT). It is used to estimate lifetime at operating temperature from accelerated tests at higher temperatures.
Bathtub curve: A curve showing how the failure rate changes over time. It consists of the early-failure, random-failure and wear-out periods and is shaped like a bathtub.
Electromigration: The movement of metal atoms in interconnects caused by electric current. It creates voids and hillocks that lead to open or short circuits.
ESD (electrostatic discharge): A sudden discharge of static electricity from a charged person or object. Applied to an IC pin it can destroy gate oxides and other structures, so I/O pins have protection circuits.
FIT rate: A unit of failure rate: 1 FIT is one failure per billion (10⁹) device-hours. It is used for parts with very low failure rates, such as semiconductors.
Hot carrier injection (HCI): Degradation in which carriers accelerated by the strong field near the drain are injected into the gate insulator, shifting the threshold voltage and reducing drive current.
Latch-up: A condition in which a parasitic thyristor structure in a CMOS circuit turns on and a large current keeps flowing between supply and ground. It is prevented by well-contact placement, guard rings and similar measures.
MTTF (mean time to failure): The average time until a non-repairable product fails. It is used as an indicator of product lifetime.
NBTI (negative bias temperature instability): A degradation phenomenon in which the magnitude of a pMOS threshold voltage gradually increases under negative gate voltage at high temperature.
Soft error: A temporary flip of data stored in memory or flip-flops caused by neutrons from cosmic rays, alpha particles and the like. The device is not damaged, so rewriting restores correct operation.
TDDB (time-dependent dielectric breakdown): A phenomenon in which an insulating film under sustained voltage eventually breaks down even below its breakdown voltage. It is used to evaluate the lifetime of gate oxides and the like.
Weibull distribution: A probability distribution widely used to analyze lifetime data. Its shape parameter can represent early-failure, random-failure and wear-out behavior.

Design and industry

LSI design flow and EDAPractice questions →

Clock gating: A low-power design technique that stops the clock to idle circuit blocks, avoiding wasted switching power.
DRC (design rule check): Verification that checks whether a layout follows the geometric rules required for manufacturing, such as line widths and spacings.
FPGA: A chip whose logic configuration the user can rewrite after manufacture. It is used for prototypes, low-volume products and ASIC verification.
High-level synthesis (HLS): Automatically generating RTL from an algorithm written in C, C++ or similar. It is used in developing FPGAs and accelerators.
Logic synthesis: The design step that converts a circuit described in RTL into a netlist made of gates from a cell library.
LVS: Short for layout versus schematic: checking that the connectivity extracted from the layout matches the schematic or netlist. It is always run before tape-out, along with DRC.
Netlist: Data describing the elements (cells) of a circuit and how they are connected. It is the output of logic synthesis and the input to place-and-route and timing analysis.
PDK (process design kit): The set of design data a foundry gives to designers, including design rules, device models, cell libraries and verification rule decks.
Place and route: The design step that arranges cells on the chip (placement) from the netlist produced by logic synthesis and determines the wiring between them (routing).
RTL (register-transfer level): A design abstraction that describes circuits by how data moves and is processed between registers. It is written in Verilog or VHDL and serves as the input to logic synthesis.
SPICE: A circuit simulator that calculates voltages and currents in transistor-level circuits in detail using device models. It is used for analog design and cell characterization.
STA (static timing analysis): A method that calculates the delay of every path in a circuit without test patterns and checks that timing constraints are met.
Standard cell: A pre-designed, pre-verified building block such as a logic gate or flip-flop. Cells share a common height so automatic place-and-route can line them up to build large circuits.
Tape-out: Handing over the finished, verified layout data to manufacturing for mask making. The name comes from the days when data was delivered on magnetic tape.

Cleanrooms and equipmentPractice questions →

Airborne molecular contamination (AMC): Gaseous contaminants in the air such as acids, alkalis and organics. Particle filters cannot remove them, so chemical filters are used.
Downflow: A cleanroom airflow method that sends clean air in one direction from the entire ceiling to the floor, quickly carrying generated particles away under the floor.
EFEM: Short for equipment front end module: the unit at the front of a tool that opens FOUPs and transfers wafers into the tool in a clean environment. It includes load ports and a transfer robot.
FFU (fan filter unit): A unit combining a fan with a high-efficiency filter. Arrays of them in the cleanroom ceiling blow clean air downward.
FOUP: A sealed container for transporting and storing 300 mm wafers.
HEPA filter: A high-efficiency air filter that captures at least 99.97% of 0.3 µm particles. Filters that capture even finer particles are ULPA filters.
ISO 14644-1: The international standard that defines cleanroom cleanliness classes by the number of airborne particles. The smaller the number, the cleaner.
Mini-environment: Keeping only the small space around the wafers highly clean. Sealed carriers such as FOUPs combined with EFEMs on the tools lower the cleanliness required of the room as a whole, reducing cost.
OHT (overhead hoist transport): Vehicles that run along ceiling rails and automatically carry FOUPs between tools. They are the backbone of automated transport in 300 mm fabs.
ULPA filter: A high-performance air filter that captures even finer particles than a HEPA filter. It is used in the ceilings of high-cleanliness cleanrooms.

Environment, health and safetyPractice questions →

Abatement system: Equipment that removes hazardous substances from tool exhaust gas by combustion, adsorption, water scrubbing and the like.
GHS: The internationally harmonized system that communicates chemical hazards with pictograms and precautionary statements.
Local exhaust ventilation: Equipment that draws in gases and mists at their source, such as tools handling chemicals, and exhausts them. It keeps workers from inhaling hazardous substances.
Lockout/tagout (LOTO): A procedure that isolates energy sources such as power and gas before maintenance and fits locks and tags so no one can accidentally restore them during the work.
Lower explosive limit (LEL): The lowest concentration in air at which a flammable gas can burn or explode. Gas detectors are often set to alarm at a percentage of this level.
Oxygen deficiency: A condition in which the oxygen concentration in air falls below 18%. It tends to occur where large amounts of nitrogen are used or in confined spaces, and can cause unconsciousness within a few breaths.
Perfluorocarbons: Also called PFCs. Fluorinated gases such as CF4 and C2F6 used in etching and chamber cleaning. Their greenhouse effect is very large.
Risk assessment: Identifying the hazards of tasks or chemicals, estimating the size of the risks and deciding countermeasures in order of priority.
RoHS Directive: The EU regulation restricting the use of specific hazardous substances such as lead and mercury in electrical and electronic equipment.
SDS (safety data sheet): A document describing the hazards of a chemical, how to handle it, first-aid measures and more.

Semiconductor industry and marketPractice questions →

ASIC (application-specific integrated circuit): An LSI designed specifically for one application or customer. It beats general-purpose chips on performance and power, but high development costs suit it to high-volume uses.
Dennard scaling: The rule that shrinking transistor dimensions and supply voltage by the same factor gives faster, denser circuits at constant power density. It broke down in the mid-2000s when voltages could no longer be lowered easily.
Discrete semiconductor: The category of semiconductor products that perform one function as a single device, such as diodes, individual transistors and power MOSFETs, as opposed to integrated circuits.
Fabless: A company model that owns no fabrication plant and focuses on designing and selling semiconductors.
Foundry: A company or business model that specializes in manufacturing semiconductors designed by other companies.
IDM (integrated device manufacturer): A semiconductor company that does everything in-house, from design through front-end and back-end manufacturing to sales.
Moore's law: The empirical rule that the number of transistors on an integrated circuit doubles about every two years. It has served as a target for semiconductor scaling.
MPW (multi-project wafer): Prototyping several customers' designs together on one wafer (one mask set). Sharing the expensive mask cost makes it popular with universities and startups.
OSAT: A company that provides back-end services such as semiconductor assembly and testing under contract.
Silicon cycle: The recurring boom-and-bust pattern of the semiconductor market driven by supply and demand. One cause is that fabs take years to build, so supply lags changes in demand.
SoC (system on chip): An LSI that integrates the functions a system needs, such as CPU, GPU, memory controller and communications, on one chip. The heart of a smartphone is a typical example.

Advanced packaging (3D and chiplets)Practice questions →

2.5D packaging: Placing several chips side by side on an intermediate substrate such as a silicon interposer and connecting them with dense, fine wiring. It is used, for example, to connect GPUs and HBM.
3D packaging: Stacking chips vertically and connecting them with TSVs or hybrid bonding. Shorter connections improve speed and power, but heat removal becomes a challenge.
Chiplet: A small chip made for a specific function. Several chiplets are connected inside one package to build a larger system.
CoWoS: TSMC's 2.5D packaging technology, which places logic chips and HBM side by side on a silicon interposer. It is widely used for AI GPUs and similar products.
HBM: High Bandwidth Memory. Multiple DRAM dies stacked with TSVs, achieving very high bandwidth through an extremely wide bus.
Hybrid bonding: A technique that directly bonds copper electrodes and dielectric surfaces without bumps, providing huge numbers of connections at extremely fine pitch.
Microbump: A bump far smaller than an ordinary solder ball, used to connect TSV-stacked chips or chips to an interposer. The pitch is a few tens of micrometers.
Redistribution layer (RDL): A wiring layer formed on a chip or wafer surface to route pads out to the positions of the external terminals. It is used in fan-out packages and interposers.
Silicon interposer: A silicon intermediate substrate that holds chips side by side and connects them densely with fine wiring. It is used to connect GPUs and HBM, among other things.
TSV (through-silicon via): An electrode that passes through the silicon substrate. It connects stacked chips vertically over a short distance.
UCIe: Short for Universal Chiplet Interconnect Express: an industry-standard die-to-die interface intended to let chiplets from different companies connect to each other.