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What is SDC?

A format for timing constraints that describes clock periods and waveforms, input and output delays, timing exceptions and so on. Written as Tcl commands, it is shared by logic synthesis, place-and-route and STA tools.

Japanese name: SDC

SDC appears in 3 practice questions across 2 topics, including IC design flow and EDA, Timing analysis and CDC.

Field: Timing analysis and CDC

Try it: questions about SDC

In timing constraints (SDC), which setting specifies margin subtracted from the clock period to allow for expected clock jitter, skew and the like?

  1. AClock uncertainty
  2. BDose
  3. CAspect ratio
Show answer and explanation

Answer: A. Clock uncertainty

Clock uncertainty is a setting that subtracts margin in timing analysis for clock jitter and, before place-and-route, expected skew. With a 1 ns period and 50 ps of uncertainty, data must arrive within 0.95 ns. The value is adjusted by design stage; after CTS, skew is calculated from the actual clock tree and only the jitter allowance remains. Dose and aspect ratio are manufacturing terms.

When a clock is divided by two with a divider circuit and used for another circuit, how should it be handled in SDC?

  1. AThe divider output is treated as a data signal, so it is analyzed correctly without any definition
  2. BDefine the divider output as a generated clock, specifying its relationship to the source clock (divide-by-2)
  3. CDefine the divided clock as a new asynchronous clock unrelated to the source clock
Show answer and explanation

Answer: B. Define the divider output as a generated clock, specifying its relationship to the source clock (divide-by-2)

SDC is the timing constraint description that tells the tool the clock periods and waveforms, input/output delays, exception paths and so on. If nothing is defined, the divider output is not treated as a clock and the flip-flops beyond it are not analyzed correctly. Defined as a generated clock, it is analyzed as 250 MHz when the source clock is 500 MHz, including its phase relationship to the source clock. The two are synchronous, so treating them as asynchronous drops paths that should be checked from the analysis.

SDC in the explanations

Questions that mention SDC (3)

  1. In timing constraints (SDC), which setting specifies margin subtracted from the clock period to allow for expected clock jitter, skew and the like?
  2. When a clock is divided by two with a divider circuit and used for another circuit, how should it be handled in SDC?
  3. In logic synthesis and static timing analysis, what is the description of timing conditions such as clock period and I/O delays called?

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Related terms

Jitter Clock uncertainty Aspect ratio Logic synthesis STA (static timing analysis) Yield PDK (process design kit) Asynchronous FIFO Clock domain Critical path

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