A scheme that transfers data reliably by exchanging a request (req) from the sender and an acknowledgment (ack) from the receiver. Across clock domains only req and ack are synchronized while the data is held stable, which is safe but takes several cycles or more per transfer.
Japanese name: ハンドシェイク
Handshake appears in 8 practice questions across 2 topics, including Timing analysis and CDC, I/O Interfaces & Buses.
Field: Timing analysis and CDC
Answer: C. Settle the data and set req to 1 → the receiver captures the data and sets ack to 1 → set req to 0 → set ack to 0
In a four-phase handshake, req and ack each rise and fall once, so one transfer completes with four transitions in total. The sender settles the data before raising req, and the receiver, seeing the synchronized req, captures the data and raises ack. The sender, seeing the synchronized ack, lowers req, and the receiver, seeing req fall, lowers ack. req and ack are single bits, so they can be passed safely through two-stage synchronizers. Raising req while changing the data risks the receiver capturing a value in transition.
Answer: A. Synchronization of req and ack makes a round trip, so each transfer takes many cycles, making it unsuited to continuous high-volume transfer
In a four-phase handshake, req takes two synchronization cycles to reach the receiver and ack two cycles to return to the sender, and returning each to 0 takes the same again, so one transfer takes 8 or more cycles in total across both domains. It therefore suits data passed occasionally, such as control register settings. The data stays stable throughout the transfer, so errors from bit misalignment do not occur, and any frequency ratio works. For streaming data almost every cycle, use an asynchronous FIFO.
In a four-phase handshake, req and ack each rise and fall once, so one transfer completes with four transitions in total.
In a four-phase handshake using req and ack, what is the co…In a four-phase handshake, req takes two synchronization cycles to reach the receiver and ack two cycles to return to the sender, and returning each to 0 takes the same again, so one transfer takes 8 or more cycles in total across both domains.
Which is a drawback of transferring data between clock doma…For counter values, convert to Gray code so that only one bit changes; for arbitrary data, use a handshake or an asynchronous FIFO.
Each bit of 4-bit data is passed to another clock domain th…When passing a pulse from a fast domain to a slow one, stretch the pulse to well beyond the receiving period, or use toggle synchronization or a handshake.
A pulse that is 1 for only one cycle (2 ns) in a 500 MHz cl…When the spacing cannot be guaranteed, use a handshake that waits for the receiver's response, or an asynchronous FIFO.
What constraint applies when passing pulses from a fast clo…As an Amazon Associate I earn from qualifying purchases.
Asynchronous FIFO Clock domain AXI Synchronizer Metastability Gray code FPGA Clock uncertainty Critical path CRPR (clock reconvergence pessimism removal)