What is High-level synthesis (HLS)?
Automatically generating RTL from an algorithm written in C, C++ or similar. It is used in developing FPGAs and accelerators.
Field: LSI design flow and EDA
High-level synthesis (HLS) in the explanations
High-level synthesis takes behavioral descriptions written in C/C++ and automatically decides allocation of operators and registers and the order of operations (scheduling), generating RTL.
What is the technology called that automatically generates …
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Related terms
RTL (register-transfer level) Clock gating DRC (design rule check) FPGA Logic synthesis LVS Netlist PDK (process design kit) Place and route SPICE