What is Gate-level simulation?
Simulation of the post-synthesis or post-layout netlist, optionally with delay information, to catch problems invisible at RTL.
Field: HDL & Verification
Gate-level simulation in the explanations
Gate-level simulation exercises the actual gates and flip-flops, and with each gate's and wire's delay supplied in SDF format, delay-related problems also show up.
What is the main purpose of simulating the post-synthesis o…
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Related terms
Netlist RTL (register-transfer level) X-optimism Asynchronous reset Blocking assignment Combinational loop Constrained random verification Four-state logic Generate statement Hardware description language (HDL)