What is 2D materials?

Layered materials that remain stable at a thickness of one to a few atomic layers. Semiconductors such as MoS2 can form extremely thin channels that are difficult with silicon, so they are being researched for future ultra-scaled transistors.

Japanese name: 2次元材料

2D materials appears in 4 practice questions across 2 topics, including Advanced transistors (FinFET and GAA), Etching.

Field: Advanced transistors (FinFET and GAA)

What 2D materials are

2D materials are one or a few layers taken from layered crystals in which atoms are strongly covalently bonded within each plane while the planes are held together by weak van der Waals forces. Typical examples are graphene (carbon), hexagonal boron nitride (hBN, an insulator) and the semiconducting transition metal dichalcogenides (TMDs). TMDs combine a transition metal such as molybdenum or tungsten with a chalcogen such as sulfur or selenium; one layer of MoS2 is about 0.65 nm thick. Graphene has no bandgap, so TMDs are the main candidates for transistor channels.

Why they suit ultra-thin channels

Suppressing short-channel effects requires a channel that is thin compared with the gate length. When silicon is thinned below a few nanometers, scattering from surface roughness sharply lowers mobility, and small thickness variations shift the threshold voltage. 2D materials have no dangling bonds on their surfaces and their layer thickness is fixed by the material, so they remain semiconducting even below 1 nm. They are therefore candidates for making nanosheet GAA and CFET channels even thinner, with MoS2 studied for n-type and WSe2 for p-type devices.

Difficult contacts and gate dielectrics

High contact resistance with metal electrodes has been a major problem for 2D-material transistors. In 2021 researchers from MIT, TSMC, National Taiwan University and others reported that semimetallic bismuth contacts greatly reduce the contact resistance to monolayer MoS2. Meanwhile, the absence of dangling bonds works against gate dielectric formation: precursors for atomic layer deposition (ALD) adsorb poorly on the surface, so high-k films do not grow uniformly, and seed layers and other techniques are being studied.

Challenges for volume production

Forming uniform, low-defect monolayer films over a whole 300 mm wafer is still difficult, and when films grown at high temperature on another substrate are transferred, wrinkles, contamination and tears become problems. Achieving good p-type performance and controlling conduction by doping as in silicon are also challenges. As of the mid-2020s, 2D-material channels are being researched for generations beyond silicon nanosheets.

Try it: questions about 2D materials

For transistors with channels made of 2D materials such as MoS2, what is the main reason it is hard to deposit a uniform high-k gate dielectric by atomic layer deposition (ALD)?

  1. A2D materials are metals and react with the dielectric
  2. BTheir surfaces have almost no dangling bonds, so there are few sites where ALD precursors can adsorb and start film growth
  3. CThe surfaces of 2D materials are very rough, so ALD precursors cannot reach deep areas
Show answer and explanation

Answer: B. Their surfaces have almost no dangling bonds, so there are few sites where ALD precursors can adsorb and start film growth

Because 2D materials have no dangling bonds on their layer surfaces, they keep their mobility even below 1 nm thickness. The same property means ALD precursors hardly adsorb chemically on the surface, so films nucleate as islands at defects and grain boundaries and do not form thin, uniform dielectrics. Plasma-based methods tend to damage the layer, so approaches such as first forming a thin nucleation layer are being studied.

Among 2D materials, why are transition metal dichalcogenides such as MoS2, rather than graphene, mainly studied as channels for logic transistors?

  1. AGraphene has no bandgap, so a gate voltage cannot shut off the current well enough
  2. BGraphene is only stable at a thickness of 1 cm or more
  3. CGraphene is an insulator that does not conduct electricity
Show answer and explanation

Answer: A. Graphene has no bandgap, so a gate voltage cannot shut off the current well enough

Graphene has very high mobility but no bandgap, so current flows even in the off state and the on/off current ratio stays small. Transition metal dichalcogenides such as MoS2 and WSe2 are semiconductors with a bandgap even as a single layer, and they work as transistors with channels about 0.65 nm thick. They are therefore studied as the next candidates for thinning channels beyond silicon nanosheets.

FAQ

Why isn't graphene used as a transistor channel?

Graphene has no bandgap, so a gate voltage cannot shut off the current well enough. For logic transistors, transition metal dichalcogenides with a bandgap, such as MoS2 and WSe2, are being studied.

Why do 2D-material channels keep their mobility even when very thin?

Their surfaces have no dangling bonds and their thickness is uniform at the atomic level, so the surface-roughness scattering and thickness variation seen in ultra-thin silicon are much weaker.

What are the main challenges for 2D-material transistors?

Contact resistance with metals, uniform deposition of gate dielectrics, large-area low-defect films, p-type performance and doping control.

2D materials in the explanations

Questions that mention 2D materials (4)

  1. For transistors with channels made of 2D materials such as MoS2, what is the main reason it is hard to deposit a uniform high-k gate dielectric by atomic layer deposition (ALD)?
  2. Among 2D materials, why are transition metal dichalcogenides such as MoS2, rather than graphene, mainly studied as channels for logic transistors?
  3. Which correctly describes materials such as molybdenum disulfide (MoS2), researched as channel materials for future ultra-small transistors?
  4. Which research-stage etching method neutralizes plasma-generated ions before they hit the wafer, suppressing charging and UV damage?

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Related terms

Mobility Plasma GAA (gate-all-around) ALD CFET (complementary FET) DTCO (design-technology co-optimization) EOT (equivalent oxide thickness) FD-SOI (fully depleted SOI) FinFET Gate-last (replacement metal gate)

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