What is Clock and data recovery (CDR)?
A receiver circuit that extracts clock timing from transitions in the received data and decides each bit, removing the need for a dedicated clock wire.
Field: I/O Interfaces & Buses
Clock and data recovery (CDR) in the explanations
So in high-speed serial links, a CDR circuit watches where the data switches between 0 and 1, generates a clock of matching frequency and phase with a PLL or similar, and samples the data in the middle of each bit.
What is the role of the clock and data recovery (CDR) circu…Long runs of 0s or 1s make the receiver's CDR lose timing and shift the average signal voltage, preventing correct decisions.
What has been the purpose of 8b/10b encoding (sending 8 dat…The receiver's CDR is designed to track this slow variation and still capture the data.
What is the purpose of spread-spectrum clocking (SSC), used…
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Related terms
PCI Express PLL (phase-locked loop) 8b/10b encoding Spread-spectrum clocking (SSC) 128b/130b encoding AXI Bit error rate (BER) Characteristic impedance Compute Express Link (CXL) Credit-based flow control