What is Logic synthesis?
The design step that converts a circuit described in RTL into a netlist made of gates from a cell library.
Field: LSI design flow and EDA
Logic synthesis in the explanations
Logic synthesis converts a behavioral description of a circuit written in RTL into connection information (a netlist) of logic gates and flip-flops from a cell library.
Which correctly describes logic synthesis?It requires no test patterns and guarantees equivalence for all input combinations, so it is used to check circuits before and after logic synthesis and place and route.
Which technique confirms mathematically, without simulation…Logic synthesis therefore builds circuits around NAND and NOR, and NAND flash is so named because its series-connected cells resemble a NAND structure.
When is the output of a two-input NAND gate 0?
Questions that mention Logic synthesis (9)
- Which correctly describes logic synthesis?
- Which technique confirms mathematically, without simulation, that a circuit's logic has not changed before and after logic synthesis?
- In logic synthesis and static timing analysis, what is the description of timing conditions such as clock period and I/O delays called?
- When is the output of a two-input NAND gate 0?
- Which is the correct order of a typical digital LSI design flow?
- Which correctly describes standard-cell design?
- Which correctly describes a netlist?
- What does "EDA" refer to?
- What is the task called of circuit-simulating standard cell delay and power across various input transition times, load capacitances, voltages and temperatures and compiling the results into tables?
Related terms
Place and route Netlist RTL (register-transfer level) STA (static timing analysis) CMOS Standard cell Clock gating DRC (design rule check) FPGA High-level synthesis (HLS)