DRAM

Learn about the DRAM 1T1C cell, why refresh is needed and how reading works through multiple-choice questions.

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DRAM: key points

DRAM stores one bit with one transistor and one capacitor. Its simple cell structure makes high density easy, so it is widely used as computer main memory.

The charge in the capacitor is gradually lost through leakage current, so the data must be rewritten periodically (refresh). Reading also disturbs the cell's charge, so the data is amplified by a sense amplifier and then written back.

All DRAM questions (50)

  1. Which correctly describes the structure of a typical 1-bit DRAM memory cell?
  2. Why does DRAM need periodic refresh operations?
  3. Which correctly describes the read operation of DRAM?
  4. Which pair of three-dimensional structures has been used in DRAM cells to secure capacitor capacitance?
  5. Which correctly describes a property of DRAM?
  6. What does 'DDR (double data rate)' in DDR SDRAM mean?
  7. In a DRAM cell array, which line connects to the gates of the cell transistors and selects the row to be read or written?
  8. How does the data retention time of DRAM cells generally change as temperature rises?
  9. Which correctly describes a soft error in memory?
  10. Compared with SRAM, which is a characteristic of DRAM?
  11. Which correctly describes redundancy repair, used to improve DRAM yield?
  12. What does an error-correcting code (ECC) used in memory do?
  13. In DRAM, why is access time shorter when the same row (page) is accessed repeatedly?
  14. Why are high-k materials such as zirconium oxide used for the dielectric film of DRAM capacitors?
  15. Which correctly describes the self-refresh mode of DRAM?
  16. How much is an 8 Gbit DRAM chip in bytes?
  17. What does the CAS latency (CL) of DRAM mean?
  18. What is the main use of the DRAM standard called LPDDR?
  19. Which is a characteristic of GDDR, used as graphics memory for GPUs?
  20. What is the main purpose of burying the gate electrode in a trench in the silicon substrate (buried word line) in recent DRAM cell transistors?
  21. In DRAM, what is the main reason for splitting the address into row and column addresses and supplying them in turn through the same pins?
  22. What is the main purpose of dividing the inside of a DRAM into multiple banks?
  23. Why is the voltage change on the bit line very small when DRAM is read?
  24. Which correctly describes the idea of 3D DRAM, under research and development as a way to increase future DRAM capacity?
  25. In DRAM, what is the phenomenon in which repeatedly activating one row in a short time can flip data in adjacent rows?
  26. Which correctly describes the main leakage paths that determine the data retention time of DRAM cells?
  27. What does F mean in '6F²', used to express DRAM cell area?
  28. In DRAM access, what is the operation called that closes the open row and returns the bit lines to an intermediate voltage to prepare for activating the next row?
  29. Which function, adopted in DDR5, corrects errors inside the DRAM chip?
  30. What is the performance limitation called that arises because improvements in memory bandwidth and latency have not kept up with improvements in processor performance?
  31. What does "RAM (random access memory)" in DRAM mean?
  32. In PCs and servers, what is DRAM mainly used for?
  33. What is the component called in which several DRAM chips are mounted on a small board that plugs into a PC as memory?
  34. What does the "S" (synchronous) in SDRAM indicate?
  35. Which trio correctly names the three major manufacturers holding large shares of the global DRAM market?
  36. In typical DRAM standards, which is closest to the period within which every cell must be refreshed once? (Normal temperature range)
  37. What does the DRAM timing parameter tRCD represent?
  38. Which correctly describes a DRAM burst transfer?
  39. Which is closest to the peak bandwidth of one channel of DDR4 memory with a data rate of 3,200 MT/s and a 64-bit data bus?
  40. What is the main effect of running PC memory in dual-channel mode?
  41. Which correctly describes a "rank" on a DRAM module?
  42. How many 8-bit-wide (x8) DRAM chips are needed per rank to form a 64-bit data bus (without ECC)?
  43. In most current PC processors, where is the memory controller that controls DRAM located?
  44. What is commonly required by DRAM standards when the chip temperature is in the high range (for example, above 85 °C)?
  45. As DRAM capacity grows, what tends to become a problem with respect to refresh?
  46. In DRAM cell arrays, which bit-line arrangement places the paired bit lines side by side within the same array?
  47. Which correctly describes the idea of "8n prefetch" used in memories such as DDR4 SDRAM?
  48. In DDR-family DRAM, which feature places termination resistors inside the DRAM chip, with controllable on/off, to suppress signal reflections?
  49. Some DRAM cells have a data retention time that irregularly switches between longer and shorter values over time. What is this phenomenon called?
  50. Why is a boosted voltage (VPP), higher than the supply voltage, used to drive DRAM word lines?

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