HDL & Verification

Learn Verilog and SystemVerilog basics with multiple-choice questions: synthesizable code, blocking versus nonblocking assignments, unintended latches, state machines, testbenches and assertions.

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HDL & Verification: key points

Digital circuits are written in hardware description languages (HDLs) such as Verilog and SystemVerilog. The code looks like a program, but it describes hardware that operates concurrently. HDLs have their own rules: which constructs can be synthesized into circuits, when to use blocking versus nonblocking assignments, and how missing conditions create unintended latches.

Whether a circuit is correct is checked with a testbench that drives inputs. From writing state machines and automatically checking properties with assertions to measuring verification completeness with coverage and generating circuits from C with high-level synthesis, this topic covers the basics of designing and verifying with HDLs.

All HDL & Verification questions (50)

  1. What is a major difference between a description written in an HDL such as Verilog and a software program in a language such as C?
  2. What is the purpose of a module in Verilog?
  3. What is the difference between wire and reg in Verilog?
  4. What circuit does the Verilog assign statement above represent?
  5. What circuit does logic synthesis create from the Verilog above?
  6. How does Verilog's nonblocking assignment (<=) behave?
  7. In the code above, a = 0 and b = 1 just before a rising clock edge. What are a and b after the edge?
  8. Intending a two-stage shift register, someone wrote the code above with blocking assignments (=). What goes wrong?
  9. What is the common guideline for choosing assignment types in Verilog?
  10. What does writing "always @(*)" mean in Verilog?
  11. Intending combinational logic, someone wrote the code above. What problem can occur?
  12. Intending combinational logic, someone writes the code above. What does logic synthesis produce?
  13. Why does the code above create a latch, and what is the fix?
  14. Which coding style is commonly used to prevent unintended latches in combinational always blocks?
  15. Which Verilog construct is ignored by logic synthesis and does not become hardware (a simulation-only construct)?
  16. When the code above, which counts the 1s in 8-bit d, is synthesized, what kind of circuit results?
  17. What type of reset does the code above have, and how does it behave?
  18. What is the difference between synchronous and asynchronous resets?
  19. In circuits using asynchronous reset, why is reset release (the 0-to-1 transition) synchronized to the clock through two flip-flops before distribution?
  20. What is the basic structure of a state machine written in an HDL?
  21. In the state machine above, why does the second always block begin with "next = state;"?
  22. What characterizes a Mealy state machine?
  23. What is a characteristic of one-hot encoding for state machine states?
  24. For a state machine with three states, how many flip-flops are needed to store the state (binary encoding / one-hot encoding)?
  25. In the 4-bit counter above, when count is 15 and a rising clock edge arrives, what does count become?
  26. In Verilog, two 8-bit signals a and b are added and assigned to an 8-bit signal s (assign s = a + b;). What should be watched for?
  27. Intending a to be signed -1, someone wrote the code above, and gt became 1. Why?
  28. Which set of values makes up the four-state logic used in Verilog simulation?
  29. In simulation, a register without reset starts as X. What happens in the real chip?
  30. In the code above, when sel is X, Verilog simulation selects b for y. Why is this a problem for verification?
  31. Which statement about tri-state descriptions that output Z (high impedance) in an HDL is generally correct?
  32. Which describes a testbench used in HDL verification?
  33. What is the period of the clock generated by the testbench code above (time unit 1 ns)?
  34. In a testbench, changing a design input with a blocking assignment at the same instant as the rising clock edge can cause problems. Which pairs the reason with a fix correctly?
  35. What characterizes a self-checking testbench?
  36. What is the purpose of a reference (golden) model written in C or similar in verification?
  37. What is the main purpose of dumping simulation results to a file in a format such as VCD?
  38. Why should the random seed be recorded in tests that use random inputs?
  39. Which describes constrained random verification in SystemVerilog?
  40. Which describes regression testing in circuit design?
  41. What is an advantage of SystemVerilog's logic type?
  42. What is the advantage of using SystemVerilog's always_ff and always_comb instead of Verilog's always?
  43. What is the advantage of writing a module with a parameter as above?
  44. What does the generate statement above do?
  45. What is the role of a lint tool in HDL verification?
  46. What is the main purpose of simulating the post-synthesis or post-layout gate-level netlist with delay information?
  47. What is a structure like the code above, where a combinational output feeds back to its own input without passing through a flip-flop, called, and why should it be avoided?
  48. When the code above is synthesized for an FPGA, how is it generally implemented?
  49. In combinational logic, how does a long if/else-if chain compare with a case statement whose conditions are mutually exclusive?
  50. What is the difference between Verilog's equality operators "==" and "==="?

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