SRAM and flash memory

Check the 6-transistor SRAM cell, the differences between NAND and NOR flash, and SLC/MLC/TLC with multiple-choice questions.

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SRAM and flash memory: key points

SRAM holds data in a latch made of two cross-coupled inverters. It needs no refresh and is fast, so it is used for CPU caches, but each bit takes up more area.

Flash memory is non-volatile: data remains even when the power is off. There is NAND flash, suited to high-capacity storage, and NOR flash, which offers fast random reads. Storing multiple bits per cell (multi-level cells) is also advancing.

All SRAM and flash memory questions (50)

  1. Which correctly describes the structure of a typical six-transistor SRAM cell?
  2. Compared with NOR flash, which is a characteristic of NAND flash memory?
  3. In flash memory, what is the scheme that stores 3 bits of information in one memory cell called?
  4. Which correctly describes how data is written to and erased from flash memory?
  5. Which correctly describes 3D NAND flash memory?
  6. What is the main reason flash memory has a limited number of rewrite cycles?
  7. What is the purpose of wear leveling, used in SSDs and similar devices?
  8. What is the unit in which data is erased in NAND flash memory?
  9. Which correctly describes a property of SRAM?
  10. In charge-trap cells, widely used in 3D NAND, which material is commonly used for the layer that stores charge?
  11. Under which condition does the data retention of flash memory tend to degrade?
  12. In recent advanced processes, what is the most appropriate reason SRAM cell area has become harder to shrink than logic?
  13. Which technique do NAND flash controllers use to cope with the increase in read errors that comes with storing more bits per cell?
  14. What is a typical use of NOR flash memory?
  15. Which correctly describes garbage collection in an SSD?
  16. In an SRAM read, what is the operation called that charges the bit lines in advance to the supply voltage or similar?
  17. Which electron injection mechanism is mainly used for writing (programming) NAND flash memory?
  18. In NAND flash, what is the phenomenon in which repeatedly reading the same block gradually shifts the threshold voltages of cells that are not being read?
  19. In QLC (4 bits per cell) NAND flash, how many threshold voltage states must one cell distinguish?
  20. In TLC and QLC SSDs, what is the main purpose of using part of the space as SLC to absorb writes temporarily?
  21. What problem tends to occur as the supply voltage of SRAM is lowered?
  22. What is the advantage of an 8T SRAM cell, which adds read-only transistors to a 6T SRAM cell?
  23. In flash memory erase, what happens to a cell's threshold voltage when electrons are removed from the floating gate or similar layer?
  24. Which is closest to the number of layers in recent 3D NAND?
  25. In NAND flash, what is the role of the select transistors placed at both ends of the series-connected memory cells?
  26. When writing to an SRAM cell, one bit line is pulled down to 0 V to flip the cell's state. What condition is required of the access transistor?
  27. In NAND flash, which programming method applies repeated program pulses with gradually increasing voltage, checking the threshold voltage after each one?
  28. Which command notifies an SSD of space freed by files deleted by the OS, making garbage collection more efficient?
  29. Which non-volatile memory has been integrated on the same chip as logic circuits to store microcontroller programs?
  30. Which orders SLC, MLC and TLC from the most rewrite cycles to the fewest?
  31. Which correctly describes flash memory?
  32. Which memory is mainly used in USB flash drives and SD cards?
  33. How many bits does an SLC (single-level cell) flash memory store per cell?
  34. Which correctly describes an SSD compared with an HDD (hard disk drive)?
  35. What is the most appropriate main use of SRAM?
  36. In NAND flash memory, what is needed to write new data to a page that already contains data?
  37. Which correctly describes the difference between EEPROM and flash memory?
  38. Which correctly describes the static noise margin (SNM) that represents the stability of an SRAM cell?
  39. Which is closest to the typical endurance (number of rewrite cycles) of SLC NAND flash memory?
  40. Which correctly describes "bad block management" in NAND flash?
  41. Which correctly describes "overprovisioning" in an SSD?
  42. Which correctly describes "write amplification" in an SSD?
  43. What is the basic unit for reading and writing (programming) in NAND flash memory?
  44. Which interface standard, built on PCI Express, is widely used to connect high-speed SSDs to the host?
  45. In SRAM, which correctly describes the "data retention voltage" that sets the lower limit when the supply is lowered during standby to reduce leakage?
  46. In a 6T SRAM cell, which design is needed so that the cell contents are not flipped during a read (to prevent read upset)?
  47. Which is an example of a "write assist" technique to prevent SRAM write failures at low voltage?
  48. In multi-level (MLC or TLC) NAND flash, why are the bit patterns assigned to adjacent threshold-voltage states chosen to differ by only one bit?
  49. In 3D NAND, what is the structure called in which the edge of the stack is shaped into steps so that each layer's word line can be connected?
  50. In 3D NAND, what is the main advantage of placing peripheral circuits such as sense amplifiers beneath the memory array (CMOS under Array and similar)?

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