A timing exception telling STA that a path may take several clock cycles to transfer data. When setup is set to N cycles, hold is usually set to N − 1 to move the hold check edge back to its original position.
Japanese name: マルチサイクルパス
Multicycle path appears in 3 practice questions across 1 topic, including Timing analysis and CDC.
Field: Timing analysis and CDC
Answer: C. +0.6 ns
A multicycle path of 2 moves the capturing edge from one period later to two periods later. The required time is 2 × 2.0 − 0.1 = 3.9 ns and the arrival time is 3.3 ns, so the slack is +0.6 ns. −1.4 ns is calculated with the normal single cycle, and +2.6 ns allows three cycles' worth of time. A multicycle path must be set only after the designer has confirmed that the circuit actually captures only every two cycles, for example via an enable signal.
Answer: A. Because the hold check edge also shifts later along with setup and becomes far too strict, so it must be moved back to its original position
By default, STA checks hold at the edge one before the setup capture edge. Making setup two cycles moves the hold check edge from time 0 to one period later, so with a 2.0 ns period the data would violate hold unless it arrived 2.0 ns or more late. Specifying a hold multicycle path of N − 1 = 1 moves the check edge back to time 0, giving the same conditions as an ordinary path. It does not remove the hold check.
A multicycle path of 2 moves the capturing edge from one period later to two periods later.
In a circuit running on a 2.0 ns clock, a path has a data a…Specifying a hold multicycle path of N − 1 = 1 moves the check edge back to time 0, giving the same conditions as an ordinary path.
When a setup multicycle path of N (N ≥ 2) is set, a hold mu…A path that captures once every two cycles should stay in the analysis as a multicycle path with extended time.
For which path is it appropriate to set a false path (set_f…As an Amazon Associate I earn from qualifying purchases.
STA (static timing analysis) Setup time Slack False path Asynchronous FIFO Clock domain Clock uncertainty Critical path CRPR (clock reconvergence pessimism removal) Handshake