Advanced packaging (3D and chiplets)

Check 3D integration and advanced packaging technologies such as chiplets, TSVs (through-silicon vias) and HBM with multiple-choice questions.

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Advanced packaging (3D and chiplets): key points

As scaling alone has become less able to raise performance, technologies that combine several chips in one package are attracting attention. Building systems from small chips divided by function (chiplets) also has advantages in yield and cost.

3D integration, which stacks chips vertically with TSVs, and 2.5D integration, which places a processor and HBM side by side on an interposer, are used in high-performance chips for AI.

All Advanced packaging (3D and chiplets) questions (50)

  1. Which correctly describes chiplets?
  2. Which correctly describes a TSV (through-silicon via)?
  3. Which correctly describes HBM (High Bandwidth Memory)?
  4. Which correctly describes the role of the silicon interposer used in 2.5D packaging?
  5. Which correctly describes hybrid bonding?
  6. Which correctly describes a feature of fan-out wafer-level packaging (FOWLP)?
  7. Which industry-standard die-to-die interface aims to let chiplets from different companies connect to each other?
  8. Which is especially likely to be a challenge in 3D packaging, which stacks chips vertically?
  9. Which correctly describes SiP (system in package)?
  10. In flip-chip connections, what is the main advantage of using copper pillars (Cu pillars) instead of solder balls?
  11. What is the wiring layer called that is formed on a chip or wafer surface to route electrode positions to the positions of external terminals?
  12. Which approach, instead of a large silicon interposer, embeds small pieces of silicon only at the chip-to-chip connection areas to achieve high-density wiring?
  13. Which is a correct advantage of glass substrates, being considered in place of organic materials for next-generation large package substrates?
  14. What is the technology called that mounts optical transceiver components close to switch ICs and the like in the same package, shortening electrical wiring to reduce power?
  15. Among hybrid bonding methods, which allows only chips judged good in test to be selected and bonded to the target wafer?
  16. What are the bumps called, far smaller than ordinary solder balls, used to connect chips stacked with TSVs and to connect chips to interposers?
  17. In AI GPUs, what is the main reason the GPU chip and HBM are placed side by side on one silicon interposer?
  18. In 3D NAND, which is a correct advantage of making the memory cell array and peripheral circuits on separate wafers and bonding them together?
  19. What is the material called that is placed between a chip and a heat spreader to fill microscopic gaps and improve heat transfer?
  20. What is the data transfer capacity that can be secured per unit length of chip edge called, emphasized as a performance metric for chiplet interconnects?
  21. Which correctly describes the difference between 2.5D and 3D packaging?
  22. In HBM, what is the typical number of DRAM dies stacked in one stack?
  23. What is the concept called that integrates chips made with different manufacturing processes and materials into one package?
  24. Which correctly describes the typical TSV formation process?
  25. What is the main aim of manufacturing packages all at once on large rectangular panels instead of round wafers?
  26. To stack chips with TSVs, approximately how thin are wafers ground from the back?
  27. Which correctly describes the benefits expected from using chiplets?
  28. Which correctly describes the conditions required of the surfaces to be joined in hybrid bonding?
  29. Which correctly describes the role of the base die (logic die) at the bottom of an HBM stack?
  30. For high-power AI packages, which is a correct example of cooling methods being considered and introduced?
  31. Which is a basic advantage of 3D packaging, which stacks chips vertically?
  32. What is the problem called in which the speed of supplying data from memory cannot keep up with improvements in processor compute performance, limiting overall performance?
  33. Which stacking method, long used in smartphone memory and elsewhere, stacks multiple chips slightly offset from one another and connects each to the substrate with wire bonding?
  34. In contrast to chiplets, what is the conventional approach called in which all the functions a system needs are built into one large chip?
  35. Advanced packaging steps that use front-end-like fine processing at the wafer level, such as forming TSVs and fine redistribution layers, sit between the front end and back end. What are they called?
  36. Which TSMC 2.5D packaging technology is widely used to place AI GPUs and HBM side by side on a silicon interposer and connect them?
  37. Which TSMC fan-out wafer-level packaging technology became widely known when it was adopted for a smartphone processor in 2016?
  38. Which is a challenge of wafer-on-wafer (W2W) bonding, which bonds entire wafers together?
  39. In 2.5D packaging, what is the main advantage of using an interposer made of redistribution layers (RDL) of organic dielectric and copper wiring instead of a silicon interposer?
  40. Through the HBM3 generation, which is the data bus width per HBM stack?
  41. When a TSV wafer is thinned to tens of micrometers and processed, which technique temporarily attaches it to a support wafer (carrier) to prevent cracking and warpage?
  42. In fan-out wafer-level packaging, what is the wafer-like form called that is rebuilt by placing diced chips with spacing on a support and embedding them in resin?
  43. Which is a challenge of moving to chiplets?
  44. What is the main aim of products that stack a cache SRAM chip on top of a processor chip with hybrid bonding?
  45. Which method is used to make silicon interposers larger than the maximum area a lithography tool can expose at once (about 26 mm × 33 mm)?
  46. Which correctly explains how copper electrodes are joined to each other in copper-dielectric hybrid bonding?
  47. In classifying TSVs by when they are formed, which approach makes TSVs after forming transistors but before forming the multilayer interconnect?
  48. Which pair of typical pitches (terminal spacing) for chip-to-chip connections is most appropriate?
  49. In manufacturing fan-out wafer-level packages, what is the problem called in which chips shift position because of resin flow or shrinkage during curing when they are encapsulated?
  50. What is the main reason for setting a keep-out zone around TSVs where no transistors are placed?

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