What is Memory barrier?
An instruction guaranteeing that memory operations before it become visible to other cores before those after it, also called a fence, such as RISC-V fence.
Field: Multicore & Synchronization
Memory barrier in the explanations
A memory barrier makes all earlier reads and writes complete (become visible to other cores) before later ones are performed.
What is the role of a memory barrier (fence) instruction?A memory barrier between the write and the read prevents it.
The two threads above run simultaneously on different cores…
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Related terms
Sequential consistency Store buffer ABA problem Acquire-release semantics Atomic instruction Barrier synchronization Bus snooping Compare-and-swap Condition variable Critical section