What is Four-state logic?

The four values used in HDL simulation: 0, 1, X (unknown) and Z (high impedance). Uninitialized or conflicting signals become X.

Field: HDL & Verification

Questions that mention Four-state logic (1)

  1. Which set of values makes up the four-state logic used in Verilog simulation?

Related terms

Verilog Asynchronous reset Blocking assignment Combinational loop Constrained random verification Gate-level simulation Generate statement Hardware description language (HDL) Lint tool Mealy machine

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