What is Place and route?
The design step that arranges cells on the chip (placement) from the netlist produced by logic synthesis and determines the wiring between them (routing).
Field: LSI design flow and EDA
Place and route in the explanations
Logic synthesis then converts it into a gate-level netlist, and place and route creates the layout on the chip.
Which is the correct order of a typical digital LSI design …It requires no test patterns and guarantees equivalence for all input combinations, so it is used to check circuits before and after logic synthesis and place and route.
Which technique confirms mathematically, without simulation…It is used as the output of logic synthesis and the input to place and route.
Which correctly describes a netlist?
Questions that mention Place and route (9)
- What is the step called that extracts wire resistance and capacitance from the layout after place and route?
- Which step at the start of place and route decides the rough placement of large circuit blocks, I/O pins, power wiring and the like?
- Which is the correct order of a typical digital LSI design flow?
- Which technique confirms mathematically, without simulation, that a circuit's logic has not changed before and after logic synthesis?
- Which correctly describes a netlist?
- What does "EDA" refer to?
- Which design approach has people design each transistor's dimensions and placement to push performance and area to the limit?
- What is it called to reflect small fixes found late in design or during manufacturing by partially modifying the existing layout, without redoing the whole design?
- In timing constraints (SDC), which setting specifies margin subtracted from the clock period to allow for expected clock jitter, skew and the like?
Related terms
Logic synthesis Netlist STA (static timing analysis) RTL (register-transfer level) Jitter Clock gating DRC (design rule check) FPGA High-level synthesis (HLS) LVS