What is STA (static timing analysis)?

A method that calculates the delay of every path in a circuit without test patterns and checks that timing constraints are met.

Field: LSI design flow and EDA

STA (static timing analysis) in the explanations

Questions that mention STA (static timing analysis) (10)

  1. Which correctly describes static timing analysis (STA)?
  2. In static timing analysis, which timing violation occurs when a signal changes too soon after the clock edge, so a flip-flop cannot correctly hold the previous data?
  3. Which is an appropriate fix when static timing analysis finds a setup violation?
  4. Why is static timing analysis performed under multiple conditions combining process variation, supply voltage and temperature?
  5. In logic synthesis and static timing analysis, what is the description of timing conditions such as clock period and I/O delays called?
  6. In static timing analysis, what is the technique called that multiplies delays by factors to add margin for transistor and wire delays varying by location even within the same chip?
  7. In static timing analysis, what is the technique called that recalculates violating paths in detail based on how signals actually propagate, removing excess pessimism from ordinary analysis?
  8. What is an advantage of a synchronous circuit, in which all flip-flops operate on a common clock?
  9. What is the step called that extracts wire resistance and capacitance from the layout after place and route?
  10. What is the task called of circuit-simulating standard cell delay and power across various input transition times, load capacitances, voltages and temperatures and compiling the results into tables?

Related terms

Logic synthesis Flip-flop Yield Place and route Standard cell Clock gating DRC (design rule check) FPGA High-level synthesis (HLS) LVS

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