What is Load-reserved/store-conditional (LR/SC)?
A pair of instructions, also called LL/SC: if another core writes the address after the load-reserved, the store-conditional fails, enabling atomic updates.
Field: Multicore & Synchronization
Load-reserved/store-conditional (LR/SC) in the explanations
Whereas CAS checks for a matching value, LR/SC checks whether any write happened, so it also detects a value that changed and changed back.
With an instruction pair such as RISC-V LR/SC (load-reserve…Examples include CAS (compare-and-swap), fetch-and-add and RISC-V's LR/SC and AMO instructions, which are the building blocks of locks and lock-free data structures.
Which describes an atomic instruction?It is prevented by pairing the pointer with a modification counter compared together, or by using LR/SC.
Which describes the ABA problem that affects lock-free data…
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Related terms
Atomic instruction Compare-and-swap ABA problem Acquire-release semantics Barrier synchronization Bus snooping Condition variable Critical section Data race Deadlock