What is Testbench?
Simulation-only code that drives inputs to the design under test and checks its outputs. Since it is never synthesized, delays, display statements and similar can be used freely.
Field: HDL & Verification
Testbench in the explanations
A testbench is HDL code that instantiates the design under test (DUT), generates clocks, resets and input signals, and observes outputs.
Which describes a testbench used in HDL verification?When the testbench updates an input at the same instant the design's flip-flops sample it, the captured value can be old or new depending on which the simulator executes first.
In a testbench, changing a design input with a blocking ass…A self-checking testbench computes or looks up the expected output for each input, compares it automatically with the design's output and reports any mismatch as an error.
What characterizes a self-checking testbench?
Questions that mention Testbench (6)
- Which describes a testbench used in HDL verification?
- What is the period of the clock generated by the testbench code above (time unit 1 ns)?
- In a testbench, changing a design input with a blocking assignment at the same instant as the rising clock edge can cause problems. Which pairs the reason with a fix correctly?
- What characterizes a self-checking testbench?
- Which Verilog construct is ignored by logic synthesis and does not become hardware (a simulation-only construct)?
- What is the difference between Verilog's equality operators "==" and "==="?
Related terms
Verilog Hardware description language (HDL) Blocking assignment SystemVerilog Slip Logic synthesis RTL (register-transfer level) Comparator Asynchronous reset Combinational loop