CPUs and architecture

Check CPU basics such as pipelining, cache memory and the von Neumann architecture with multiple-choice questions.

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CPUs and architecture: key points

A CPU processes a program by repeatedly fetching, decoding and executing instructions. Most computers use the von Neumann architecture, in which programs and data are stored in the same main memory.

Performance-enhancing techniques include pipelining, which overlaps stages of instruction processing; caches, which bridge the speed gap with main memory; and parallel processing with multiple cores. Semiconductor scaling has supported all of these advances.

All CPUs and architecture questions (50)

  1. What is the main purpose of pipelining in a CPU?
  2. What is the main purpose of cache memory?
  3. Which is a characteristic of a von Neumann computer?
  4. What is the main purpose of putting multiple processor cores on one chip (multicore)?
  5. Which is a characteristic of RISC (reduced instruction set computer)?
  6. What is the period of a 1 GHz clock?
  7. What is the purpose of branch prediction in a CPU?
  8. What is the main reason GPUs are well suited to matrix operations and AI training and inference?
  9. If the cache access time is 10 ns, the main memory access time is 100 ns, and the cache hit rate is 90%, what is the average access time?
  10. In a CMOS circuit, if only the supply voltage is halved with everything else unchanged, what happens to dynamic power consumption?
  11. What do names like ARM, x86 and RISC-V mainly refer to?
  12. Which is a characteristic of RISC-V?
  13. What is the processor design called that issues and executes multiple instructions simultaneously in one clock cycle?
  14. Which cache holds the results of translating virtual addresses into physical addresses to speed up address translation?
  15. Which dedicated circuit is built into smartphone SoCs and similar chips to perform AI inference quickly and with low power?
  16. In a typical computer, which lists the memory hierarchy from fastest to slowest access?
  17. Approximately how many instructions per second can a processor with a 2 GHz clock and an average CPI (clocks per instruction) of 0.5 execute?
  18. If 90% of a program can be parallelized, what is the theoretical maximum speedup when it runs on an unlimited number of processors?
  19. Which scheme performs the same operation on multiple data items simultaneously with a single instruction?
  20. Which CPU configuration combines high-performance cores and power-efficient cores and uses them according to the workload?
  21. Which technique examines instruction dependencies and executes ready instructions in an order different from the program order to improve performance?
  22. Which CPU mechanism temporarily suspends the current task to give priority to handling requests such as those from external devices?
  23. Which mechanism transfers data directly between peripherals and memory without going through the CPU?
  24. Which LSI integrates a CPU, memory and peripherals such as timers and ADCs on one chip and is used to control appliances and equipment?
  25. In a multicore CPU, which mechanism keeps data consistent when the caches of several cores hold data for the same address?
  26. Which technique reduces CPU power consumption by dynamically changing operating frequency and supply voltage according to the load?
  27. Which is an example of vulnerabilities revealing attacks that exploit traces of speculative execution left in the cache to infer data that should not be accessible?
  28. Which metric indicates the amount of heat generated under a standard heavy load, used as a guide for CPU cooling design?
  29. Which metric indicates the number of instructions executed per clock?
  30. What is the problem called in which power and heat constraints prevent all circuits on a chip from running at full performance at the same time?
  31. What does CPU stand for?
  32. Which correctly describes a CPU with a clock frequency of 3 GHz?
  33. What does "64-bit" in "64-bit CPU" mainly refer to?
  34. What is the correct basic order in which a CPU processes an instruction?
  35. What is the role of the ALU (arithmetic logic unit) in a CPU?
  36. What does a CPU's program counter (PC) hold?
  37. Which correctly describes the write-back policy for caches?
  38. Which correctly describes a set-associative cache?
  39. What is the typical size of a cache line (cache block) in many current CPUs?
  40. In a pipeline, when the next instruction immediately uses the result of the previous one (a data hazard), which technique passes the result directly to the next instruction without waiting for it to be written to the register?
  41. Which correctly describes little-endian byte order?
  42. Which technique lets one CPU core process instructions from multiple threads at the same time to make better use of the core's execution units?
  43. In microcontrollers and similar devices, which scheme assigns peripheral registers to the same address space as memory and operates them with ordinary memory read/write instructions?
  44. What is the role of the watchdog timer built into microcontrollers?
  45. When a program calls a subroutine (function), which area is generally used to temporarily save the return address and similar information?
  46. Which correctly lists the "three Cs" classification of cache misses?
  47. In an out-of-order CPU, which mechanism commits (retires) the results of instructions executed out of order in the program's original order?
  48. What is the main purpose of register renaming in out-of-order CPUs?
  49. In AI accelerators and similar, which architecture arranges many multiply-accumulate units in a grid and computes matrix products by passing data from one unit to the next?
  50. Which model plots whether a program's performance is limited by compute throughput or memory bandwidth, using arithmetic intensity (operations per byte) on the horizontal axis?

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