What is Miss penalty?
The extra time needed to fetch data from the next level when a cache miss occurs, determined by the lower level's access time and the line transfer time.
Field: Memory Hierarchy
Miss penalty in the explanations
Average memory access time = hit time + miss rate × miss penalty = 2 + 0.04 × 150 = 2 + 6 = 8 cycles.
With a cache hit time of 2 cycles, a miss rate of 4% and a …Even a small miss rate badly hurts performance when the miss penalty is large.
A processor has an average CPI of 1.0 with a perfect cache.…The L1 miss penalty is the L2 average access time, 10 + 0.2 × 100 = 30 ns.
With an L1 hit time of 1 ns and miss rate of 5%, an L2 hit …
Questions that mention Miss penalty (9)
- With a cache hit time of 2 cycles, a miss rate of 4% and a miss penalty of 150 cycles, what is the average memory access time in cycles?
- A processor has an average CPI of 1.0 with a perfect cache. Each instruction makes 1.3 memory accesses on average, with a 2% miss rate and a 100-cycle miss penalty. What is the actual average CPI?
- With an L1 hit time of 1 ns and miss rate of 5%, an L2 hit time of 10 ns and local miss rate of 20%, and main memory access time of 100 ns, what is the average memory access time?
- What is the effect of increasing a cache's line size?
- When inserting software prefetch instructions, which statement about how far ahead to fetch (the prefetch distance) is correct?
- In a multilevel cache with an L2 below the L1, what is the L2's main role?
- If the cache hit rate is 95%, what is the miss rate?
- Which technique, when fetching a missed line from memory, sends the word the CPU needs first and the rest afterward?
- Why must cache designs be compared by average memory access time rather than miss rate alone?
Related terms
Average memory access time Cycles per instruction (CPI) Spatial locality Prefetching Write-allocate Cache line Capacity miss Compulsory miss Conflict miss Direct-mapped cache