The contract specifying in what order a core's reads and writes to multiple addresses may be observed by other cores. Examples include sequential consistency, x86 TSO and the weak models of Arm and RISC-V.
Field: Multicore & Synchronization
A memory consistency model defines which reorderings can occur and is the contract that lets programmers write correct synchronization.
What does a memory consistency model define?Store buffer Total store order (TSO) ABA problem Acquire-release semantics Atomic instruction Barrier synchronization Bus snooping Compare-and-swap Condition variable Critical section