The time from an input change to the resulting output change. For logic ICs it is measured between the points where input and output cross 50% of their swing, and is specified separately as tPLH (output low to high) and tPHL (output high to low). It grows with load capacitance.
Japanese name: 伝搬遅延
Propagation delay appears in 2 practice questions across 2 topics, including How to read datasheets, Testing and inspection.
Field: How to read datasheets
Answer: C. The time from an input change until the output changes from L to H, measured between the 50% points of the swings
tPLH is the propagation delay when the output changes from L to H, and tPHL is the delay when it changes from H to L; the two are generally not equal. The reference points are usually 50% (VDD/2) of the input and output swings respectively, though 1.5 V is sometimes used for TTL families. The time to go from 10% to 90% of the swing is the rise time, a separate parameter from propagation delay. Delay varies with load capacitance, supply voltage and temperature, so read it together with the test conditions in the table.
tPLH is the propagation delay when the output changes from L to H, and tPHL is the delay when it changes from H to L; the two are generally not equal.
Which is the common definition of the propagation delay tPL…AC test measures timing characteristics: input-to-output propagation delay, setup and hold times, and output rise and fall times.
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