DRAM that stacks memory cells vertically in many layers to increase capacity without relying only on planar shrinking. Handling the capacitor is the biggest challenge, and as of the mid-2020s it is still in research and development.
Japanese name: 3D DRAM
3D DRAM appears in 3 practice questions across 1 topic, including DRAM.
Field: DRAM
DRAM stores one bit with one transistor and one capacitor (1T1C). The capacitor needs a certain capacitance to give a readable signal, so as cells shrink the capacitor has become a thin, deep cylinder with a very high aspect ratio. Shrinking the cell transistor also makes it harder to keep leakage low and word-line resistance acceptable. DRAM has grown in capacity by shrinking planar dimensions, but continuing that alone is becoming difficult.
NAND flash went 3D by stacking hundreds of word-line layers and etching vertical holes through all of them at once to form strings of cells. The same is hard for DRAM because every cell needs a capacitor, and today's capacitors are so tall that they cannot simply be stacked. Researchers are therefore studying structures in which the cell transistor and capacitor are laid on their sides in each layer and many layers are stacked. A sideways cell takes more area per layer, though, so many layers are needed before the result beats planar DRAM in density.
For stacked sideways cells, one approach grows dozens of alternating silicon and silicon-germanium (SiGe) layers epitaxially and forms the cells from that stack. In 2025 imec and Ghent University reported growing up to 120 Si/SiGe bilayers on 300 mm wafers. Capacitorless cells are another route: the two-transistor (2T0C) cell using IGZO oxide-semiconductor transistors, reported by imec in 2020, exploits an extremely low off-current to hold charge on the parasitic capacitance of the read transistor. Oxide semiconductors can be formed at low temperature, which also makes them easier to stack above wiring layers.
In multilayer epitaxy, strain from the lattice mismatch between Si and SiGe tends to create defects, and this gets harder as the layer count grows. Lateral etching and deposition must also reach uniformly deep into tall structures. With sideways capacitors the cell area per layer grows, so whether enough layers can be stacked at low cost is key. As of the mid-2020s, 3D DRAM is being researched by memory makers and research institutes, and no volume-production date has been set.
Answer: A. Stacking memory cells vertically to increase capacity without relying only on planar scaling
DRAM is approaching the limits of capacitor aspect ratio and cell-transistor scaling. 3D DRAM, which stacks cells vertically as 3D NAND does, is therefore under development, with concepts such as laying transistors and capacitors horizontally and stacking many layers, or capacitorless cells. It would raise capacity without relying on planar scaling, but manufacturing technology is still in development.
Answer: A. 3D DRAM stacks the memory cells themselves vertically within one chip, while HBM stacks finished DRAM chips with TSVs
HBM stacks several finished DRAM chips connected by TSVs and places them near the processor for high bandwidth; it is chip stacking. 3D DRAM, like 3D NAND, stacks layers of memory cells vertically within a single chip to raise capacity without relying only on planar shrinking. As of the mid-2020s, 3D DRAM is in research and development.
HBM stacks finished DRAM chips vertically with TSVs, so it is chip stacking. 3D DRAM stacks the memory cells themselves vertically within a single chip. They are different technologies.
Each DRAM cell needs a capacitor to store charge, and today's capacitors are very tall. Researchers are studying cells laid on their sides and stacked, and cells without capacitors.
As of the mid-2020s it is in research and development, and no volume-production date has been set. Multilayer crystal growth, processing of deep structures and stacking many layers at low cost are the challenges.
3D DRAM, which stacks cells vertically as 3D NAND does, is therefore under development, with concepts such as laying transistors and capacitors horizontally and stacking many layers, or capacitorless cells.
Which correctly describes the idea of 3D DRAM, under resear…3D DRAM, like 3D NAND, stacks layers of memory cells vertically within a single chip to raise capacity without relying only on planar shrinking.
Which correctly describes the difference between 3D DRAM an…For 3D DRAM, researchers are studying structures that lay the transistor and capacitor on their sides in each layer, and capacitorless cells that hold charge on the parasitic capacitance of oxide-semiconductor transistors such as IGZO.
What is the main reason 3D DRAM is hard to achieve simply b…As an Amazon Associate I earn from qualifying purchases.
DRAM (dynamic random-access memory) 3D NAND Aspect ratio HBM 1T1C cell Bank Bit line CAS latency DDR SDRAM DIMM