A method that manufactures many packages at once on a large rectangular panel instead of a round wafer. It uses area efficiently and can lower cost, but warpage, die shift over large areas and equipment standardization are challenges.
Japanese name: パネルレベルパッケージ(PLP)
Panel-level packaging (PLP) appears in 2 practice questions across 1 topic, including Advanced packaging (3D and chiplets).
In fan-out wafer-level packaging (FOWLP), singulated dies are placed on a round carrier, fixed in molding resin, and covered with redistribution layers. Panel-level packaging (PLP) carries out similar steps on a large rectangular panel closer to those used for printed circuit boards and displays. Panel sizes include 510 mm × 515 mm and 600 mm × 600 mm; a 600 mm square panel has an area of 360000 mm², about 5 times that of a 300 mm diameter wafer (about 70700 mm²). Processing more packages at once lowers the cost per package.
When rectangular packages are laid out on a round wafer, regions near the edge cannot hold a whole package. The larger the package, the larger the fraction of this edge waste. For large packages tens of millimeters on a side, such as those for AI, the usable fraction of a 300 mm wafer drops sharply, whereas a rectangular panel can be filled almost to its edges. The spread of large packages carrying many chiplets and HBM stacks is one reason for the interest in PLP.
The larger the panel, the larger the warpage from resin cure shrinkage and thermal expansion mismatch, and the larger the shift of dies during molding (die shift). Uniform film thickness and exposure over the whole panel are also hard, and wafer lithography and plating tools cannot be used as they are, so panel-specific equipment is needed. Panel sizes are not yet standardized across the industry, which complicates equipment and material development. Wafer processes cannot simply be scaled up.
PLP first came into use for relatively small packages; in 2021 the Korean company nepes Laweh announced volume production of fan-out packages on 600 mm square panels. Since the mid-2020s it has also been developed as a way to cut the cost of large AI packages. On the other hand, panel processes generally have more difficulty producing fine wiring than wafer processes, so how to handle the parts that need the finest wiring is also under study.
Answer: C. The larger the package, the larger the fraction of edge area on a round wafer that cannot hold a package, whereas a rectangular panel can be filled almost to its edges
When rectangular packages are laid out on a round wafer, regions near the edge cannot hold a whole package, and the fraction grows with package size. Panel-level packaging (PLP) uses rectangular panels, so even packages tens of millimeters on a side can be laid out with little waste, and a 600 mm square panel has about 5 times the area of a 300 mm wafer. This is why PLP is being developed to cut the cost of large AI packages carrying many chiplets and HBM stacks. Warpage, die shift and uniformity over large areas become harder, however.
The basic steps are similar, but FOWLP uses a round wafer-shaped carrier and PLP uses a large rectangular panel. PLP can process more packages at once with less edge waste, which helps lower cost, but warpage and uniformity are harder to control.
600 × 600 = 360000 mm², and a 300 mm wafer is π × 150² ≈ 70700 mm², so the panel is about 5 times larger.
Warpage over large areas, die shift during molding, uniformity of film thickness and exposure, development of panel equipment, and standardization of panel sizes.
Panel-level packaging (PLP) uses rectangular panels, so even packages tens of millimeters on a side can be laid out with little waste, and a 600 mm square panel has about 5 times the area of a 300 mm wafer.
Why does panel-level packaging (PLP) gain more advantage ov…Panel-level packaging is being developed to cut costs for fan-out and large AI packages.
What is the main aim of manufacturing packages all at once …As an Amazon Associate I earn from qualifying purchases.
HBM 2.5D packaging 3D packaging Chiplet CoWoS Glass core substrate Hybrid bonding Microbump Redistribution layer (RDL) Silicon interposer