A group of flip-flops driven by the same clock, or by clocks with a fixed frequency and phase relationship. Passing a signal between clock domains that are asynchronous to each other requires a synchronizer.
Japanese name: クロックドメイン
Clock domain appears in 5 practice questions across 1 topic, including Timing analysis and CDC.
Field: Timing analysis and CDC
Answer: A. Because the receiving side may capture a momentary glitch on the combinational output as a valid value
Within the same clock domain, glitches settle before the next clock edge and cause no problem. When captured by an asynchronous clock, however, the edge can come at any time, so a momentary 1 pulse on a signal that should be 0 can be captured. The rule is therefore that signals crossing domains come directly from a flip-flop output in the sending domain. Metastability does not occur every time, and CDC verification tools also flag combinational logic in front of synchronizers.
Answer: A. The bits may be captured in different cycles, so an intermediate value such as 1111 or 0000 may be received
For each bit, a two-stage synchronizer does not determine whether a change is captured at the current edge or the next one. In a change from 0111 to 1000 all four bits change, so for one cycle the receiver may get a value in which only some bits have their new value, such as 1111, 0000 or 0100. If the receiver uses that value, it malfunctions. Metastability resolves to 0 or 1 over time. For counter values, convert to Gray code so that only one bit changes; for arbitrary data, use a handshake or an asynchronous FIFO.
Within the same clock domain, glitches settle before the next clock edge and cause no problem.
Why must the output of combinational logic in the sending c…As an Amazon Associate I earn from qualifying purchases.
Synchronizer Metastability Handshake Asynchronous FIFO Flip-flop Gray code Clock uncertainty Critical path CRPR (clock reconvergence pessimism removal) False path