What is Blocking assignment?
Verilog's "=" assignment, which updates the left side immediately so the next statement sees the new value. Used in combinational always blocks and testbenches.
Field: HDL & Verification
Blocking assignment in the explanations
With blocking assignment (=), line 1 sets a to 1, and line 2 gives b the new a, 1, so both end up as 1.
In the code above, a = 0 and b = 1 just before a rising clo…With blocking assignment, line 1 immediately updates q1 to d, and line 2 gives q2 the updated q1, which is d.
Intending a two-stage shift register, someone wrote the cod…
Questions that mention Blocking assignment (3)
- In a testbench, changing a design input with a blocking assignment at the same instant as the rising clock edge can cause problems. Which pairs the reason with a fix correctly?
- In the code above, a = 0 and b = 1 just before a rising clock edge. What are a and b after the edge?
- Intending a two-stage shift register, someone wrote the code above with blocking assignments (=). What goes wrong?
Related terms
Testbench SystemVerilog Nonblocking assignment Shift register Asynchronous reset Combinational loop Constrained random verification Four-state logic Gate-level simulation Generate statement