English
Menu

What is Clock uncertainty?

A margin subtracted from the available time in timing analysis to account for jitter and for clock skew not yet known. It is set with set_clock_uncertainty in SDC, and before the clock tree is built it is set larger to cover skew as well.

Japanese name: クロックの不確かさ

Clock uncertainty appears in 4 practice questions across 2 topics, including Timing analysis and CDC, IC design flow and EDA.

Field: Timing analysis and CDC

Try it: questions about Clock uncertainty

On a flip-flop-to-flip-flop path, the clock-to-output delay is 0.15 ns, the maximum combinational logic delay is 2.2 ns and the setup time is 0.15 ns. Ignoring skew and clock uncertainty, what is the maximum clock frequency at which this path can operate?

  1. AAbout 425 MHz
  2. BAbout 455 MHz
  3. C400 MHz
Show answer and explanation

Answer: C. 400 MHz

The minimum clock period is the sum of the clock-to-output delay, the combinational logic delay and the setup time. 0.15 + 2.2 + 0.15 = 2.5 ns, so the maximum frequency is 1 ÷ 2.5 ns = 400 MHz. About 425 MHz comes from 2.35 ns, which leaves out the setup time, and about 455 MHz from the 2.2 ns combinational logic delay alone. The maximum frequency of the whole chip is set by the tightest of such paths, the critical path.

On a path with a clock period of 1.25 ns (800 MHz), the clock-to-output delay plus combinational logic delay totals 1.05 ns, the setup time is 0.05 ns, and the setup clock uncertainty is set to 0.05 ns. What is the setup slack?

  1. A0.15 ns
  2. B0.20 ns
  3. C0.10 ns
Show answer and explanation

Answer: C. 0.10 ns

Clock uncertainty is a margin subtracted from the available time to account for jitter and skew that is not yet determined. The required time is 1.25 − 0.05 (uncertainty) − 0.05 (setup time) = 1.15 ns and the arrival time is 1.05 ns, so the slack is 0.10 ns. 0.15 ns leaves out the uncertainty, and 0.20 ns subtracts neither the setup time nor the uncertainty. Before place and route there is no clock tree, so it is common to set a larger uncertainty that also covers skew.

Clock uncertainty in the explanations

Questions that mention Clock uncertainty (4)

  1. On a flip-flop-to-flip-flop path, the clock-to-output delay is 0.15 ns, the maximum combinational logic delay is 2.2 ns and the setup time is 0.15 ns. Ignoring skew and clock uncertainty, what is the maximum clock frequency at which this path can operate?
  2. On a path with a clock period of 1.25 ns (800 MHz), the clock-to-output delay plus combinational logic delay totals 1.05 ns, the setup time is 0.05 ns, and the setup clock uncertainty is set to 0.05 ns. What is the setup slack?
  3. In clock uncertainty settings, period jitter is often included for setup but not for hold. Why?
  4. In timing constraints (SDC), which setting specifies margin subtracted from the clock period to allow for expected clock jitter, skew and the like?

Books on Timing analysis and CDC Ad

As an Amazon Associate I earn from qualifying purchases.

Semiconductor Calculators

Phase noise to RMS jitter conversionIntegrate a phase-noise profile in dBc/Hz to get a clock's RMS phase error and RMS jitter

Related terms

Jitter Setup time Flip-flop Critical path Slack Place and route SDC Aspect ratio Asynchronous FIFO Clock domain

Back to the glossary