What is Sensitivity list?
The list in @( ) after a Verilog always that names the signals triggering the block. Omissions in combinational logic make simulation and hardware disagree.
Field: HDL & Verification
Sensitivity list in the explanations
The list inside @( ) after always is called the sensitivity list and specifies which signal changes trigger the block.
What does writing "always @(*)" mean in Verilog?A simulator runs the block only when a signal in the sensitivity list changes, so when only b changes, y keeps its stale value.
Intending combinational logic, someone wrote the code above…Because "negedge rst_n" is in the sensitivity list, the block also runs the instant rst_n falls from 1 to 0, and q becomes 0 regardless of the clock.
What type of reset does the code above have, and how does i…
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Related terms
Verilog SystemVerilog Logic synthesis Asynchronous reset Blocking assignment Combinational loop Constrained random verification Four-state logic Gate-level simulation Generate statement