What is Netlist?

Data describing the elements (cells) of a circuit and how they are connected. It is the output of logic synthesis and the input to place-and-route and timing analysis.

Field: LSI design flow and EDA

Netlist in the explanations

Questions that mention Netlist (5)

  1. What is it called to automatically generate test patterns that detect faults from a circuit's netlist?
  2. Which correctly describes a netlist?
  3. Which is the correct order of a typical digital LSI design flow?
  4. Which correctly describes logic synthesis?
  5. Which are the typical formats of layout data handed to manufacturing for mask making?

Related terms

Logic synthesis Place and route RTL (register-transfer level) ATPG (automatic test pattern generation) Fault coverage Tape-out SPICE Clock gating DRC (design rule check) FPGA

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