What is SerDes?

Serializer/deserializer: a circuit that turns parallel on-chip data into a fast serial bit stream for transmission and restores the parallel data at the receiver. It is the heart of high-speed serial physical layers.

Field: I/O Interfaces & Buses

SerDes in the explanations

Questions that mention SerDes (7)

  1. What is the role of a SerDes (serializer/deserializer) in high-speed serial links?
  2. What is a typical use of a shift register, which chains flip-flops in series and moves data one bit to the next on each clock?
  3. In testing high-speed serial interfaces, which method loops the chip's transmitter output back to its receiver so the chip itself verifies communication?
  4. How does communication in PCI Express work?
  5. High-speed links such as 100-gigabit Ethernet are sometimes built by bundling, for example, four 25 Gb/s lanes. Which describes this approach?
  6. In AI systems with many GPUs, why are dedicated high-speed GPU-to-GPU links (such as NVIDIA NVLink) used in addition to PCI Express?
  7. Which statement is correct about PCI Express link power saving (the L0s and L1 states of ASPM)?

Related terms

PCI Express Shift register PAM4 GPU 128b/130b encoding 8b/10b encoding AXI Bit error rate (BER) Characteristic impedance Clock and data recovery (CDR)

Back to the glossary