What is ECC (error-correcting code)?

A scheme that adds redundant bits to data so that bit errors can be detected and corrected on readout. It is used in server memory, flash memory and inside DDR5 chips, among others.

Field: DRAM

ECC (error-correcting code) in the explanations

Questions that mention ECC (error-correcting code) (8)

  1. What does an error-correcting code (ECC) used in memory do?
  2. How many 8-bit-wide (x8) DRAM chips are needed per rank to form a 64-bit data bus (without ECC)?
  3. When an even parity bit is added to the 7-bit data 1011001, what is the parity bit?
  4. Which correctly describes a soft error in memory?
  5. Which function, adopted in DDR5, corrects errors inside the DRAM chip?
  6. Some DRAM cells have a data retention time that irregularly switches between longer and shorter values over time. What is this phenomenon called?
  7. In multi-level (MLC or TLC) NAND flash, why are the bit patterns assigned to adjacent threshold-voltage states chosen to differ by only one bit?
  8. What design challenge arises from the probabilistic nature of writing in STT-MRAM?

Related terms

Soft error Refresh TLC (triple-level cell) Gray code STT-MRAM 1T1C cell Bank Bit line CAS latency DDR SDRAM

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