What is X-optimism?
In HDL simulation, the tendency for conditions containing unknown X to resolve to definite values instead of propagating X, hiding bugs.
Field: HDL & Verification
X-optimism in the explanations
This is called X-optimism and is countered by coding styles that propagate X or by adding assertions that detect X.
In the code above, when sel is X, Verilog simulation select…RTL simulation is fast but cannot reveal unknown-value problems hidden by X-optimism, or cases where synthesis produced a circuit different from the description.
What is the main purpose of simulating the post-synthesis o…
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Related terms
Verilog Netlist RTL (register-transfer level) Gate-level simulation Asynchronous reset Blocking assignment Combinational loop Constrained random verification Four-state logic Generate statement