Three-dimensional integration in which transistor layers are built one after another on a single wafer. Layers can be connected far more finely than by bonding finished chips, but the upper layers must be made at low temperature. Also called sequential 3D integration.
Japanese name: モノリシック3D集積
Monolithic 3D integration appears in 1 practice question across 1 topic, including Advanced transistors (FinFET and GAA).
3D packaging with TSVs or hybrid bonding stacks separately made chips or wafers by bonding them. The density of connections between layers is then set by the bonding alignment accuracy and the size of the connections. In monolithic 3D integration, after the first transistor layer is built, a thin semiconductor layer is formed or bonded on top, and the second transistor layer is made with lithography aligned to the first. Layers can be connected with vias about the size of ordinary wiring vias, dense enough to split individual transistors or logic gates between tiers.
Normal transistor fabrication uses temperatures around 1000 °C, for example to activate implanted dopants. Applying such heat while building an upper layer would degrade the silicide and wiring of the lower layer and change its transistors. The upper-layer process must therefore be kept at roughly 500 °C or below, and techniques such as short laser anneals and low-temperature crystal growth have been developed. CEA-Leti has reported transistors and circuits made with a maximum temperature of 500 °C since around 2020.
A feature of monolithic 3D integration is that different kinds of devices can be stacked in different layers; placing memory or sensor circuits above logic shortens wiring and improves speed and power. Among CFETs, which stack nMOS and pMOS vertically, the approach that builds the top tier sequentially on a layer bonded over the bottom tier is a form of monolithic 3D integration. Note, however, that in the CFET field the approach that patterns both tiers from one stack in a continuous flow is called a "monolithic CFET", so the terminology needs care.
Upper-layer transistors made at low temperature have difficulty matching the performance of lower-layer devices that can use high-temperature steps, and removing heat from between the layers is harder. Because layers are built in sequence on one wafer, it is impossible to test each layer and combine only good ones, so a defect in any layer lowers overall yield. Design tools spanning layers are still maturing. In memory, 3D NAND, which stacks cell layers on one wafer, is in volume production, but logic products with many stacked transistor layers were not yet common as of the mid-2020s.
Answer: C. The upper layer is built directly on the lower one and aligned by lithography, so layers can be connected with vias about the size of ordinary wiring vias
When chips or wafers are bonded, connection density is set by bonding alignment accuracy and connection size. In monolithic 3D integration, a thin semiconductor layer is formed or bonded on the first layer and the second transistor layer is made with lithographic alignment, so layers can be connected as finely as wiring vias. In exchange, the upper layer must be made at roughly 500 °C or below to avoid damaging the lower layer.
3D packaging bonds separately made chips, whereas monolithic 3D integration builds transistor layers in sequence on one wafer. Because upper layers are aligned by lithography, layers can be connected as finely as ordinary vias.
High temperatures would degrade the silicide and wiring of the lower layers that already exist and change their transistor characteristics. As a guide, the process is kept at about 500 °C or below.
The two terms are used almost interchangeably. "Sequential" emphasizes that the layers are built one at a time.
In monolithic 3D integration, a thin semiconductor layer is formed or bonded on the first layer and the second transistor layer is made with lithographic alignment, so layers can be connected as finely as wiring vias.
What is the main reason monolithic 3D integration can conne…As an Amazon Associate I earn from qualifying purchases.
3D packaging Interconnect via 2D materials CFET (complementary FET) DTCO (design-technology co-optimization) EOT (equivalent oxide thickness) FD-SOI (fully depleted SOI) FinFET GAA (gate-all-around) Gate-last (replacement metal gate)