What is PCI Express?
A high-speed serial expansion interface connecting the CPU with GPUs, SSDs, network cards and more, also written PCIe. Lanes are bundled for bandwidth, and speed roughly doubles each generation.
Field: I/O Interfaces & Buses
PCI Express in the explanations
NVMe (NVM Express) is designed to drive flash efficiently over PCI Express and supports up to 64K command queues in parallel.
Which interface standard, built on PCI Express, is widely u…This is why PCI Express 3.0 nearly doubled effective throughput while raising the signaling rate only from 5 to 8 GT/s.
Which is closest to the efficiency of the 128b/130b encodin…One PCI Express lane consists of a transmit differential pair and a receive differential pair, four wires in all, and carries data in both directions simultaneously.
Which describes a "lane" in PCI Express?
Questions that mention PCI Express (29)
- Which interface standard, built on PCI Express, is widely used to connect high-speed SSDs to the host?
- Which is closest to the efficiency of the 128b/130b encoding adopted from PCI Express 3.0 onward?
- Which describes a "lane" in PCI Express?
- What is closest to the effective one-direction bandwidth of a PCI Express 3.0 x16 link (8 GT/s per lane, 128b/130b encoding)?
- For PCI Express generations 3 through 6, how does the per-lane signaling rate change with each generation?
- What is a characteristic of PAM4 (four-level pulse amplitude modulation), adopted in PCI Express 6.0?
- What happens when an x4 PCI Express SSD is plugged into a full-length x16 slot on a motherboard (assuming the slot is wired for at least x4)?
- Which statement about the structure of PCI Express is correct?
- How does communication in PCI Express work?
- What does the PCI Express data link layer do about bit errors during transmission?
- How are the registers and memory of a PCI Express device made accessible to the CPU?
- What is a characteristic of MSI (message-signaled interrupts) used in PCI Express?
- Which describes hot plugging, supported by USB and some PCI Express setups?
- What is the purpose of spread-spectrum clocking (SSC), used in PCI Express and elsewhere?
- What does it mean that a PCI Express lane is full duplex?
Related terms
SerDes GPU Compute Express Link (CXL) 128b/130b encoding PAM4 NRZ Clock and data recovery (CDR) 8b/10b encoding NVMe Throughput