What is LVS?
Short for layout versus schematic: checking that the connectivity extracted from the layout matches the schematic or netlist. It is always run before tape-out, along with DRC.
Field: LSI design flow and EDA
LVS in the explanations
Confirming that the connectivity of the schematic and layout match is called LVS (Layout Versus Schematic).
Which correctly describes DRC (design rule check) in layout…A PDK contains the process's design rules, simulation models for transistors and other devices, rule files for DRC and LVS, basic cells and more.
What is the set of design data, including design rules, dev…Sign-off includes, in addition to timing and DRC/LVS, analysis of voltage drop in the power network (IR drop) and electromigration due to current density in wires.
In the final check before tape-out (sign-off), which power-…
Questions that mention LVS (4)
- Which correctly describes DRC (design rule check) in layout verification?
- What is the set of design data, including design rules, device models and cell libraries, that a foundry provides to designers called?
- In the final check before tape-out (sign-off), which power-network analysis is performed alongside timing verification?
- In layout verification, which check looks for electrical connection errors, such as inputs left floating (connected to nothing) or supplies shorted together?
Related terms
DRC (design rule check) Foundry PDK (process design kit) Tape-out IR drop Electromigration Clock gating FPGA High-level synthesis (HLS) Logic synthesis