What is Cache line?
The unit in which data moves between a cache and the level below, also called a cache block. Many CPUs use 64 bytes, and the low address bits give the position (offset) within the line.
Field: Memory Hierarchy
Cache line in the explanations
DDR4 uses a burst length of 8 and DDR5 16; on a 64-bit DDR4 bus that is 8 × 8 bytes = 64 bytes—exactly one CPU cache line.
Which correctly describes a DRAM burst transfer?Coherence protocols such as MESI tag each cache line with states like Modified, Shared or Invalid and invalidate other copies on writes to keep data consistent.
In a multicore CPU, which mechanism keeps data consistent w…With j in the inner loop, consecutive addresses are read in order, so the rest of each 64-byte cache line fetched on a miss is used right away.
Scanning the 2D C array a[i][j] with j in the inner loop, a…
Questions that mention Cache line (9)
- What is the typical size of a cache line (cache block) in many current CPUs?
- In the loop above, an int is 4 bytes, a cache line is 64 bytes, and the array is not cached and starts on a line boundary. Without prefetching, what is the miss rate for reading the array?
- What is the role of the valid bit attached to each cache line?
- In the MESI protocol, what does it mean when a cache line is in the Modified (M) state?
- Which correctly describes a DRAM burst transfer?
- In a multicore CPU, which mechanism keeps data consistent when the caches of several cores hold data for the same address?
- Scanning the 2D C array a[i][j] with j in the inner loop, as above, tends to be faster than with i in the inner loop. Why?
- Which correctly lists the four states of the MESI cache coherence protocol?
- Which describes false sharing in a multithreaded program?
Related terms
False sharing Spatial locality Prefetching MESI protocol TLB (translation lookaside buffer) Average memory access time Capacity miss Compulsory miss Conflict miss Direct-mapped cache