What is AXI?
An on-chip bus from Arm's AMBA specifications that connects blocks in an SoC, with five independent channels and a VALID/READY handshake. Variants include AXI4-Lite and AXI4-Stream.
Field: I/O Interfaces & Buses
AXI in the explanations
AXI has five channels: read address (AR), read data (R), write address (AW), write data (W) and write response (B).
What is a characteristic of the AXI bus?Data at consecutive addresses, such as a cache-line fill, is often handled together, so AXI can send just the starting address and a length and then stream the data as a burst.
What is the advantage of burst transfers in AXI?AXI tags requests with IDs and allows several to be outstanding, so data keeps returning during the latency and bandwidth is used well.
In AXI, what is the advantage of issuing the next read requ…
Questions that mention AXI (6)
- What is a characteristic of the AXI bus?
- In the VALID/READY handshake used on each AXI channel, when is data transferred?
- What is the advantage of burst transfers in AXI?
- In AXI, what is the advantage of issuing the next read request without waiting for the previous one's response (having multiple outstanding requests)?
- Which bus from Arm's AMBA specifications is widely used to connect blocks such as CPUs, memory controllers and peripherals inside an SoC?
- What is AXI4-Lite mainly used for?
Related terms
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