Semiconductor Calculators
Free browser calculators for the numbers chip engineers use every day: dies per wafer and yield, lithography resolution, timing slack and more.
Die per wafer and yield calculatorGross dies, yield (Poisson, Murphy, negative binomial) and cost per good die, with a wafer mapLithography resolution and depth of focus calculatorResolution (half-pitch), depth of focus and pitch splits from wavelength, NA and k1Setup and hold timing calculatorSetup and hold slack and maximum clock frequency for a flip-flop to flip-flop pathMOSFET I-V characteristics (ID–VDS)Change Vth, W/L and λ and see the ID–VDS curves and the operating point: region, ID, gm and roQuiz set builderPick topics and a question count to get a shareable quiz link for classes and trainingJunction temperature and thermal resistance calculatorJunction temperature, margin to Tj(max) and maximum power from power dissipation and thermal resistanceMemory bandwidth calculatorPeak and effective bandwidth of DDR, LPDDR, GDDR and HBM from transfer rate and bus widthADC SNR and effective number of bits (ENOB)SNR and effective number of bits of an ADC from resolution, clock jitter and oversamplingAmdahl's law and parallel speedupSpeedup and parallel efficiency from the parallel fraction and processor count, by Amdahl's and Gustafson's lawsCache address breakdown and average memory access timeTag, index and offset bits and average memory access time from cache size, line size and associativityCMOS power consumption (dynamic and static)Dynamic and static power from activity factor, capacitance, voltage, frequency and leakage, plus the power after DVFSPN junction built-in potential and depletion widthBuilt-in potential, depletion width, peak field and junction capacitance of a PN junction from doping and reverse biasThermal oxide thickness (Deal-Grove model)Silicon oxide thickness and consumed silicon from temperature, time, dry or wet ambient and orientation, using the Deal-Grove modelOn-chip interconnect RC delayWire resistance and capacitance, distributed RC delay and delay with driver and load from metal, width, thickness, spacing, dielectric constant and lengthPhase noise to RMS jitter conversionIntegrate a phase-noise profile in dBc/Hz to get a clock's RMS phase error and RMS jitterPDN target impedance and decoupling capacitorsTarget impedance from supply voltage, allowed ripple and current step, plus the self-resonant frequency and effective band of decoupling capacitors