A condition in which a parasitic thyristor structure in a CMOS circuit turns on and a large current keeps flowing between supply and ground. It is prevented by well-contact placement, guard rings and similar measures.
Field: Reliability
Isolation from the substrate lowers junction capacitance and leakage and eliminates latch-up.
Which correctly describes the SOI (silicon on insulator) st…A low-resistance p+ substrate underneath also shunts parasitic-thyristor current and limits potential differences between wells, suppressing CMOS latch-up.
What is an advantage of a wafer with a lightly doped p-type…Surface doping stays low to suit transistor characteristics, while the heavily doped depths suppress punch-through and latch-up (parasitic thyristor action).
In CMOS well formation, what is a well called in which high…CMOS Junction capacitance (depletion capacitance) FD-SOI (fully depleted SOI) Oxygen precipitates (BMD) Czochralski (CZ) method Gettering Retrograde well Punch-through Arrhenius model Bathtub curve