The path with the largest delay in a circuit, which sets the maximum clock frequency. In STA it is the path with the smallest slack, and speeding up a design starts by reducing its delay.
Japanese name: クリティカルパス
Critical path appears in 2 practice questions across 2 topics, including Logic circuits, Timing analysis and CDC.
Field: Timing analysis and CDC
Answer: C. The delay of the slowest path between flip-flops (the critical path)
The clock period must be at least the clock-to-Q delay plus the path's logic delay plus setup time plus margins such as skew, so the slowest path (the critical path) sets the maximum frequency; a 1 ns total allows at most 1 GHz. Speed-up techniques include pipelining to split paths, reducing logic depth, and using stronger or low-Vth cells on slow paths.
Answer: C. 400 MHz
The minimum clock period is the sum of the clock-to-output delay, the combinational logic delay and the setup time. 0.15 + 2.2 + 0.15 = 2.5 ns, so the maximum frequency is 1 ÷ 2.5 ns = 400 MHz. About 425 MHz comes from 2.35 ns, which leaves out the setup time, and about 455 MHz from the 2.2 ns combinational logic delay alone. The maximum frequency of the whole chip is set by the tightest of such paths, the critical path.
The clock period must be at least the clock-to-Q delay plus the path's logic delay plus setup time plus margins such as skew, so the slowest path (the critical path) sets the maximum frequency; a 1 ns total allows at most 1 GHz.
In a synchronous circuit, what determines the maximum clock…The maximum frequency of the whole chip is set by the tightest of such paths, the critical path.
On a flip-flop-to-flip-flop path, the clock-to-output delay…As an Amazon Associate I earn from qualifying purchases.
Setup time Pipelining Flip-flop Clock uncertainty Asynchronous FIFO Clock domain CRPR (clock reconvergence pessimism removal) False path Handshake MTBF (mean time between failures)