Volatile memory that stores each bit in a cell of one transistor and one capacitor and needs periodic refresh before the charge leaks away. It is used as main memory in PCs and servers.
Japanese name: DRAM(ダイナミックRAM)
DRAM (dynamic random-access memory) appears in 94 practice questions across 16 topics, including DRAM, Emerging memories, Semiconductor industry and market.
Field: DRAM
DRAM stands for dynamic random-access memory. Each bit is stored in a 1T1C cell made of one transistor and one capacitor, with the presence or absence of charge on the capacitor representing 0 or 1. Cells sit in a grid at the crossings of word lines and bit lines; turning on the transistor through the word line connects the capacitor to the bit line. Random access means any address can be reached regardless of order, and dynamic refers to the fact that the stored charge slowly leaks away, so the data has to be rewritten periodically.
To read a cell, its capacitor is connected to a bit line precharged to about half the supply voltage. The charge is shared, producing a small voltage difference that a sense amplifier amplifies to decide 0 or 1. Because this disturbs the stored charge (a destructive read), the amplified voltage is written back to the cell. Charge is also lost through junction and subthreshold leakage, so every row must be read and rewritten at intervals, which is called refresh. As a guide, standards up to DDR4 require all rows to be refreshed within 64 ms in the normal temperature range and DDR5 within 32 ms, with shorter intervals at high temperature.
SRAM builds a latch from six transistors, so it needs no refresh and can be accessed in around 1 ns, but its cells are large and its cost per bit is high. DRAM's small 1T1C cell makes it roughly 20 times denser than SRAM, suiting it to large main memory, at the cost of access times of tens of nanoseconds because rows must be activated. NAND flash memory is nonvolatile, keeping data with power off, and offers even larger capacity at lower cost, but it writes and erases slowly and has a limited number of rewrite cycles. Systems therefore build a memory hierarchy with SRAM for caches, DRAM for main memory and SSDs for storage.
DRAM products include DDR SDRAM for PCs and servers, low-power LPDDR for smartphones and similar devices, GDDR for graphics, and HBM, which stacks several dies with TSVs to provide a very wide bus. The central scaling challenge is keeping enough charge on the capacitor to read the data as cells shrink. Tall, narrow cylindrical capacitors, high-dielectric-constant (high-k) insulators and buried-word-line transistors that reduce leakage have been introduced to meet it. Higher density also brings reliability issues such as Rowhammer, where repeatedly activating a row flips data in neighboring rows.
Answer: A. One transistor and one capacitor
A DRAM cell consists of one transistor and one capacitor (1T1C), storing a bit as the presence or absence of charge on the capacitor. The capacitor is tiny—around 10 fF—so 0 and 1 differ by only tens of thousands of electrons. With so few components the cell is small (about 6F²), ideal for high density. Six transistors is the SRAM cell, and a floating-gate transistor is the flash memory cell.
Answer: C. Because the charge stored in the capacitor is gradually lost through leakage current
Charge on the capacitor gradually leaks away through the cell transistor's subthreshold and junction leakage. Refresh reads and rewrites each cell before its data becomes unreadable; every row must be refreshed within 64 ms up to DDR4, and within 32 ms in DDR5. During refresh, the bank cannot be accessed and power is consumed, a burden that grows with capacity. A limit on write cycles is a characteristic of flash memory.
Dynamic random-access memory. It is called dynamic because the stored charge is lost over time and must be refreshed periodically, unlike SRAM (static RAM), which keeps its data without refresh as long as power is applied.
DRAM uses a small 1T1C cell, so it can be made large and cheap, but it needs refresh and takes tens of nanoseconds to access. SRAM uses a six-transistor cell that needs no refresh and is fast, but takes more area. That is why DRAM is used for main memory and SRAM for CPU caches.
Yes. DRAM is volatile: when power is removed, refresh stops and the charge leaks away. If the chips are cooled, however, data can persist for seconds to minutes, which cold boot attacks exploit to read encryption keys from memory.
A DRAM cell consists of one transistor and one capacitor (1T1C), storing a bit as the presence or absence of charge on the capacitor.
Which correctly describes the structure of a typical 1-bit …To keep around 10 fF of capacitance as cells shrink, DRAM has made its capacitors three-dimensional: trench capacitors dug deep into the substrate, and stacked capacitors built as tall cylinders above the transistor.
Which pair of three-dimensional structures has been used in…DRAM stores data as charge and is volatile: when power is removed, the charge is not maintained and the data is lost.
Which correctly describes a property of DRAM?DRAM's small 1T1C cell (about 6F²) packs roughly 20 times denser than a 6T SRAM cell (about 120–150F²), lowering cost per bit.
Compared with SRAM, which is a characteristic of DRAM?Without this redundancy repair, high-capacity DRAM yields would be untenable.
Which correctly describes redundancy repair, used to improv…As an Amazon Associate I earn from qualifying purchases.
Refresh HBM MRAM Bit line ECC (error-correcting code) Sense amplifier Word line 3D NAND Bank 3D DRAM