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What is Synchronizer?

A circuit that aligns an asynchronous signal to the receiving clock. The basic form is two flip-flops in series, which raises the probability that metastability in the first stage resolves before the next edge.

Japanese name: 同期化回路

Synchronizer appears in 11 practice questions across 2 topics, including Timing analysis and CDC, Logic circuits.

Two-flip-flop synchronizer Source clock domain Destination clock domain Source FF FF1 FF2 Async Direct Synced output Source clock Dest. clock Metastable risk Dest. clock FF1 output Unsettled FF2 output ~1 cycle If FF1 settles before the next edge, FF2 gets the correct value
Two-flip-flop synchronizer · View in diagrams

Field: Timing analysis and CDC

Try it: questions about Synchronizer

Which path between two clock domains requires a synchronizer?

  1. ABetween a 400 MHz clock generated by a PLL and the 200 MHz clock obtained by dividing it by two
  2. BBetween clocks obtained by distributing the same clock to two regions through the clock tree
  3. CBetween clocks generated from separate oscillators, with no defined frequency or phase relationship
Show answer and explanation

Answer: C. Between clocks generated from separate oscillators, with no defined frequency or phase relationship

Clocks generated from the same source with a defined frequency ratio and phase relationship are synchronous clocks, and once STA checks setup and hold, they can be treated like ordinary paths. Clocks from separate oscillators, even if both are labeled 100 MHz, actually differ slightly in frequency, so their edge alignment changes over time and a moment inevitably comes when setup or hold cannot be met. STA cannot guarantee paths between such asynchronous clocks, so a synchronizer is needed.

How does the mean time between failures (MTBF) due to metastability change when a two-flip-flop synchronizer is extended to three stages?

  1. AThe time available for metastability to resolve increases by about one period, and MTBF grows exponentially
  2. BMTBF increases 1.5 times, in proportion to the number of stages
  3. CHow likely metastability is depends on the input side, so MTBF does not change
Show answer and explanation

Answer: A. The time available for metastability to resolve increases by about one period, and MTBF grows exponentially

Synchronizer MTBF is approximately MTBF = e^(t_r/τ) ÷ (T_0 × f_clk × f_data), where t_r is the time available for metastability to resolve and τ and T_0 are constants determined by the flip-flop's characteristics. Adding a stage extends t_r by about one period. For example, with τ = 20 ps, increasing t_r by 1 ns multiplies MTBF by e^50, more than 10^21 times. The probability of the first stage going metastable is unchanged, but the probability that it resolves before propagating further rises sharply.

Synchronizer in the explanations

Questions that mention Synchronizer (11)

  1. Which path between two clock domains requires a synchronizer?
  2. How does the mean time between failures (MTBF) due to metastability change when a two-flip-flop synchronizer is extended to three stages?
  3. Raising the clock frequency on the receiving side of a synchronizer shortens MTBF. Why?
  4. Which is a correct precaution about the connection between the first and second stages of a two-flip-flop synchronizer?
  5. Why must the output of combinational logic in the sending clock domain not be fed directly into a synchronizer in the receiving domain?
  6. Each bit of 4-bit data is passed to another clock domain through its own two-stage synchronizer. What problem can occur when the data changes from 0111 to 1000?
  7. A pulse that is 1 for only one cycle (2 ns) in a 500 MHz clock domain is passed to a 100 MHz domain through a two-stage synchronizer. What problem can occur?
  8. To pass a level signal reliably from a 400 MHz domain to a 100 MHz domain through a synchronizer, the signal width should be at least 1.5 times the receiving clock period. What is the minimum width in sending-clock cycles?
  9. Two control signals from the same sending domain are each received through a separate two-stage synchronizer and ANDed on the receiving side. What is the problem with this design?
  10. What is the state called when a flip-flop receiving an asynchronous signal violates setup or hold time and its output is temporarily neither 0 nor 1?
  11. Which is a correct way to pass multi-bit data safely to another clock domain?

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Related terms

MTBF (mean time between failures) Metastability Flip-flop Clock domain Gray code Handshake Asynchronous FIFO STA (static timing analysis) Hold time Clock uncertainty

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