LSI design flow and EDA

Check the LSI design flow from specification through RTL design, logic synthesis, place and route, and static timing analysis with multiple-choice questions.

—Your accuracy
0 / 50Questions answered
Practice this topicAll questions in this topic, in random order Weak questionsRetry only the questions you last got wrong

LSI design flow and EDA: key points

LSI design proceeds by deciding the specification, describing the circuit at register-transfer level (RTL) in a hardware description language, converting it into a netlist of gates by logic synthesis, and creating the layout by place and route.

Each stage requires simulation with EDA tools, static timing analysis (STA) and verification. The larger the design, the greater the verification effort.

All LSI design flow and EDA questions (50)

  1. Which is the correct order of a typical digital LSI design flow?
  2. Which correctly describes logic synthesis?
  3. Which correctly describes static timing analysis (STA)?
  4. Which hardware description languages are mainly used in RTL design?
  5. Which correctly describes DRC (design rule check) in layout verification?
  6. Which technique confirms mathematically, without simulation, that a circuit's logic has not changed before and after logic synthesis?
  7. Which correctly describes standard-cell design?
  8. Which correctly describes a feature of FPGAs?
  9. What is the main purpose of clock tree synthesis (CTS) in the place-and-route stage?
  10. What does 'IP (IP core)' mean in LSI design?
  11. In static timing analysis, which timing violation occurs when a signal changes too soon after the clock edge, so a flip-flop cannot correctly hold the previous data?
  12. What is the set of design data, including design rules, device models and cell libraries, that a foundry provides to designers called?
  13. Which is the representative circuit simulator that calculates voltages and currents of transistor-level circuits in detail using device models?
  14. What is the technology called that automatically generates RTL from algorithm descriptions written in C or C++?
  15. Which low-power design technique stops the clock to unused circuit blocks to reduce wasted power?
  16. Which is an appropriate fix when static timing analysis finds a setup violation?
  17. Why is static timing analysis performed under multiple conditions combining process variation, supply voltage and temperature?
  18. What is the step called that extracts wire resistance and capacitance from the layout after place and route?
  19. In verifying large SoCs, which technique runs the designed circuit on dedicated hardware or FPGAs and verifies it quickly together with software?
  20. What is it called to hand over the data for mask making to manufacturing after design and verification are complete?
  21. In the final check before tape-out (sign-off), which power-network analysis is performed alongside timing verification?
  22. Which design philosophy refines layouts and the like to make them less susceptible to manufacturing variation and defects?
  23. In analog layout, which technique splits paired transistors and places them so their centroids coincide?
  24. What is the main purpose of placing dummy patterns that do not function as circuits in empty areas of the layout?
  25. For layouts intended for double patterning, which correctly describes how design tools assign patterns?
  26. Which correctly describes a netlist?
  27. In logic synthesis and static timing analysis, what is the description of timing conditions such as clock period and I/O delays called?
  28. Which are the typical formats of layout data handed to manufacturing for mask making?
  29. Which step at the start of place and route decides the rough placement of large circuit blocks, I/O pins, power wiring and the like?
  30. In RTL verification, which metric is used to evaluate how thoroughly verification has been done?
  31. What does "EDA" refer to?
  32. Which set correctly lists companies with large shares of the global EDA tool market?
  33. In developing large LSIs, which activity is said to take a large share of the total effort?
  34. Which set correctly gives the three metrics represented by "PPA", often used to evaluate LSI designs?
  35. Which design approach has people design each transistor's dimensions and placement to push performance and area to the limit?
  36. Which approach prefabricates a common base (master) covered with transistors and designs and manufactures only the wiring layers for each product?
  37. In verification using SystemVerilog, which standard methodology is used to build reusable test environments (testbenches)?
  38. In layout verification, which check looks for electrical connection errors, such as inputs left floating (connected to nothing) or supplies shorted together?
  39. Which technique describes properties a design must satisfy (for example, "respond within 3 cycles of a request") and has them checked automatically during simulation or by formal verification?
  40. In low-power design, which standard format describes the "power intent", such as power domains, power shutoff and level shifters, separately from the circuit description?
  41. What is the verification called that uses dedicated tools to check whether synchronizers are correctly inserted where signals pass between circuits running on different clocks?
  42. What is it called to reflect small fixes found late in design or during manufacturing by partially modifying the existing layout, without redoing the whole design?
  43. Which set correctly names cells with no logic function (or auxiliary ones) placed among standard cells to fill gaps, tie well potentials and suppress supply noise?
  44. What is the task called of circuit-simulating standard cell delay and power across various input transition times, load capacitances, voltages and temperatures and compiling the results into tables?
  45. In static timing analysis, what is the technique called that multiplies delays by factors to add margin for transistor and wire delays varying by location even within the same chip?
  46. Which analysis method, rather than combining worst-case values at corners, treats delay variation as probability distributions and computes the probability of meeting timing?
  47. In timing constraints (SDC), which setting specifies margin subtracted from the clock period to allow for expected clock jitter, skew and the like?
  48. In static timing analysis, what is the technique called that recalculates violating paths in detail based on how signals actually propagate, removing excess pessimism from ordinary analysis?
  49. In analog circuit design, which technique repeatedly simulates with randomly applied transistor variations from manufacturing to estimate performance distributions and yield?
  50. Which logic simulation method computes only the parts affected when a signal value changes (an event)?

Other topics in Design and industry