What is Standard cell?
A pre-designed, pre-verified building block such as a logic gate or flip-flop. Cells share a common height so automatic place-and-route can line them up to build large circuits.
Field: LSI design flow and EDA
Questions that mention Standard cell (2)
- When standard cell height is expressed in the number of routing tracks, what is the effect of reducing the number of tracks?
- What is the task called of circuit-simulating standard cell delay and power across various input transition times, load capacitances, voltages and temperatures and compiling the results into tables?
Related terms
Logic synthesis STA (static timing analysis) Clock gating DRC (design rule check) FPGA High-level synthesis (HLS) LVS Netlist PDK (process design kit) Place and route