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Timing analysis and CDC

Check static timing analysis — setup/hold slack calculation, OCV and multicycle paths — and the design of clock domain crossings using synchronizers and asynchronous FIFOs, with multiple-choice questions.

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Timing analysis and CDC: key points

For a synchronous circuit to work correctly, data must arrive on every path between flip-flops in time to meet setup and hold times. Static timing analysis (STA) computes the slack of each path from the clock and input/output delay constraints given in SDC, accounting for skew, jitter and manufacturing variation, and finds violations.

Between asynchronous clocks, on the other hand, timing cannot be guaranteed and metastability is unavoidable. Designing and verifying clock domain crossings (CDC) that pass signals safely — with two-flip-flop synchronizers, handshakes and asynchronous FIFOs with Gray code pointers — is also a fundamental part of logic design.

All Timing analysis and CDC questions (50)
  1. In a synchronous circuit with a clock period of 2.0 ns, the launching flip-flop's clock-to-output delay is 0.2 ns, the combinational logic delay is 1.4 ns and the capturing flip-flop's setup time is 0.1 ns. With zero clock skew, what is the setup slack?
  2. On a flip-flop-to-flip-flop path, the clock-to-output delay is 0.15 ns, the maximum combinational logic delay is 2.2 ns and the setup time is 0.15 ns. Ignoring skew and clock uncertainty, what is the maximum clock frequency at which this path can operate?
  3. Which correctly describes WNS and TNS as they appear in STA reports?
  4. A path has a clock period of 1.0 ns, a clock-to-output delay of 0.1 ns, a combinational logic delay of 0.85 ns and a setup time of 0.08 ns. If the clock arrives at the capturing flip-flop 0.05 ns later than at the launching flip-flop, what is the setup slack?
  5. When the clock arrives at the capturing flip-flop later than at the launching flip-flop (positive skew), what is the effect on setup and hold?
  6. The launching flip-flop's minimum clock-to-output delay is 0.08 ns, the minimum combinational logic delay is 0.02 ns and the capturing flip-flop's hold time is 0.05 ns. If the clock arrives at the capturing flip-flop 0.1 ns later than at the launching flip-flop, what is the hold slack?
  7. A hold violation (slack −0.03 ns) is found on an ordinary path that launches and captures on the rising edge of the same clock. How is this violation affected if the clock frequency is halved?
  8. To fix a hold violation, delay buffers are inserted in the data path. What is the most important thing to check when doing this?
  9. On a path with a clock period of 1.25 ns (800 MHz), the clock-to-output delay plus combinational logic delay totals 1.05 ns, the setup time is 0.05 ns, and the setup clock uncertainty is set to 0.05 ns. What is the setup slack?
  10. In clock uncertainty settings, period jitter is often included for setup but not for hold. Why?
  11. In STA, which combination correctly gives the corner conditions mainly used to check setup and hold?
  12. For OCV derating in setup analysis, the launch clock path and data path delays are multiplied by 1.1 and the capture clock path delay by 0.9. With a launch clock path of 1.0 ns, a data path (including clock-to-output) of 1.5 ns, a capture clock path of 1.0 ns (no common portion), a period of 3.0 ns and a setup time of 0.1 ns, what is the setup slack?
  13. In STA with OCV derating, when the launch and capture clock paths share a common portion, which correctly describes CRPR (common path pessimism removal)?
  14. In a circuit running on a 2.0 ns clock, a path has a data arrival time (clock-to-output plus combinational logic delay) of 3.3 ns and a setup time of 0.1 ns. Since this path only needs to capture once every two cycles, a setup multicycle path of 2 is set. What is the setup slack?
  15. When a setup multicycle path of N (N ≥ 2) is set, a hold multicycle path of N − 1 is normally set as well. Why?
  16. For which path is it appropriate to set a false path (set_false_path)?
  17. With a 2.0 ns clock at 50% duty cycle, a path launches on the rising edge and captures on the falling edge. With a setup time of 0.1 ns and zero skew, what is the maximum allowed sum of the clock-to-output delay and combinational logic delay?
  18. With a 2.0 ns clock, a path runs from a flip-flop that launches data on the rising edge at time 0 to a latch that opens (becomes transparent) at 1.0 ns and closes at 2.0 ns. If the data arrives at the latch at 1.4 ns, how much time has been borrowed at this latch (time borrowing)?
  19. In a circuit that stops the clock with a two-input AND gate of the clock and an enable signal, what does the STA clock gating check verify?
  20. With a 2.0 ns clock, set_input_delay 0.6 ns is set on an input port. If the internal flip-flop's setup time is 0.1 ns and clock latency and skew are ignored, what is the maximum delay allowed for the on-chip path from the input port to the flip-flop?
  21. What does the value specified with set_output_delay represent?
  22. With a 2.5 ns (400 MHz) clock, set_output_delay 0.8 ns is set on an output port. If the clock-to-output delay of the flip-flop driving the port is 0.2 ns, what is the maximum delay allowed for the combinational logic and wiring from the flip-flop to the output port (ignore clock latency)?
  23. With a 1.0 ns clock, flip-flops are connected A→B→C. A→B needs 1.2 ns including clock-to-output delay and setup time, while 0.8 ns is enough for B→C. To meet setup on both by intentionally using skew, what should be done to B's clock (assume the clocks of A and C arrive at the same time)?
  24. When a clock is divided by two with a divider circuit and used for another circuit, how should it be handled in SDC?
  25. In a flip-flop with asynchronous reset, which STA check examines whether reset deassertion is too close to a clock edge?
  26. Which path between two clock domains requires a synchronizer?
  27. How does the mean time between failures (MTBF) due to metastability change when a two-flip-flop synchronizer is extended to three stages?
  28. Raising the clock frequency on the receiving side of a synchronizer shortens MTBF. Why?
  29. Which is a correct precaution about the connection between the first and second stages of a two-flip-flop synchronizer?
  30. Why must the output of combinational logic in the sending clock domain not be fed directly into a synchronizer in the receiving domain?
  31. Each bit of 4-bit data is passed to another clock domain through its own two-stage synchronizer. What problem can occur when the data changes from 0111 to 1000?
  32. Which is a correct way to pass multi-bit data safely to another clock domain?
  33. A pulse that is 1 for only one cycle (2 ns) in a 500 MHz clock domain is passed to a 100 MHz domain through a two-stage synchronizer. What problem can occur?
  34. To pass a level signal reliably from a 400 MHz domain to a 100 MHz domain through a synchronizer, the signal width should be at least 1.5 times the receiving clock period. What is the minimum width in sending-clock cycles?
  35. In toggle synchronization (a scheme in which the sending side generates and passes a level signal that inverts each time a pulse arrives), how is the original pulse recovered on the receiving side?
  36. What constraint applies when passing pulses from a fast clock domain to a slow one with toggle synchronization?
  37. In a four-phase handshake using req and ack, what is the correct signal sequence for passing one data item?
  38. Which is a drawback of transferring data between clock domains with a handshake?
  39. Why are the write and read pointers of an asynchronous FIFO converted to Gray code before being synchronized into the other domain?
  40. What is the 4-bit binary value 0110 (decimal 6) converted to Gray code?
  41. In a 16-word-deep asynchronous FIFO, why are the write and read pointers made 5 bits, one bit more than the address?
  42. In a 16-word-deep asynchronous FIFO with 5-bit Gray code pointers, what is the correct condition for detecting full on the write side?
  43. In an asynchronous FIFO, the other side's pointer is used after synchronization, so the pointer value seen is 2–3 cycles stale. What effect does this delay have on full/empty detection?
  44. In an asynchronous FIFO with a 100 MHz write side and an 80 MHz read side, the write side writes a 100-word burst at one word per cycle and the read side reads one word per cycle. There is ample idle time between bursts. What is the minimum depth needed to avoid overflow (ignore synchronization delay)?
  45. The write side writes a 120-word burst at one word per cycle at 200 MHz. The read side, on a 150 MHz clock, reads one word in only 2 out of every 3 cycles. What is the minimum depth needed to avoid overflow (ignore synchronization delay)?
  46. The write side runs at 250 MHz and the read side at 200 MHz, both transferring one word per cycle. What is the minimum calculated depth for a FIFO receiving a 64-word burst (ignore synchronization delay and round up fractions)?
  47. Which is the correct structure of a reset synchronizer that generates, from an active-low external reset, an internal reset that is "asserted asynchronously and deasserted synchronously"?
  48. Two control signals from the same sending domain are each received through a separate two-stage synchronizer and ANDed on the receiving side. What is the problem with this design?
  49. Why is checking with a CDC verification tool considered necessary even when STA and RTL simulation have been done?
  50. Why can it be a problem to leave the paths that carry an asynchronous FIFO's Gray code pointers to the other domain unconstrained (false path) just because they are asynchronous?

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