What is CHERI?
Short for Capability Hardware Enhanced RISC Instructions. An instruction-set extension that replaces pointers with capabilities, which carry the range they may point to and their permissions in addition to the address, so that out-of-bounds accesses and forged pointers are stopped in hardware. It has been developed by the University of Cambridge and SRI International. Arm made Morello, a prototype processor based on it, available to researchers in the early 2020s.
Japanese name: CHERI
CHERI appears in 1 practice question across 1 topic, including Hardware Security: Advanced Topics and Trends.
Field: Hardware Security: Advanced Topics and Trends
What a capability contains
A conventional pointer is just an address, and the hardware has no way to check what it points to. A CHERI capability carries, in addition to the address, the lower and upper bounds of the range it may point to and permissions such as read, write and execute. For 64-bit addresses the bounds are stored in compressed form so that the capability fits in 128 bits, and one more tag bit is kept outside the normal memory contents. The CPU checks the bounds and permissions on every load and store and raises an exception if they are violated, so errors such as buffer overflows stop on the spot.
FAQ
What is the difference between CHERI and MTE (Memory Tagging Extension)?
MTE compares 4-bit tags attached to memory and to pointers and finds errors probabilistically. CHERI gives each pointer its own bounds and permissions and stops out-of-bounds accesses deterministically. MTE is easier to bring to existing software, while CHERI gives stronger guarantees at the cost of larger changes to the instruction set and software.
Does CHERI eliminate all memory-safety problems?
It prevents out-of-bounds accesses and pointer forgery, but preventing use of memory after it has been freed needs additional work in the allocator. It also cannot prevent logic errors or the misuse of permissions that were legitimately granted. It is used together with other measures.