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What is Slack?

A value expressing timing margin. For setup it is required time minus arrival time, and for hold it is arrival time minus required time; a negative value means a violation.

Japanese name: スラック

Slack appears in 10 practice questions across 1 topic, including Timing analysis and CDC.

Field: Timing analysis and CDC

Try it: questions about Slack

In a synchronous circuit with a clock period of 2.0 ns, the launching flip-flop's clock-to-output delay is 0.2 ns, the combinational logic delay is 1.4 ns and the capturing flip-flop's setup time is 0.1 ns. With zero clock skew, what is the setup slack?

  1. A0.3 ns
  2. B0.4 ns
  3. C0.5 ns
Show answer and explanation

Answer: A. 0.3 ns

Setup slack is calculated as "required time − arrival time." The data arrival time is 0.2 + 1.4 = 1.6 ns and the required time is the next clock edge minus the setup time, 2.0 − 0.1 = 1.9 ns, so the slack is 1.9 − 1.6 = 0.3 ns. Being positive, it meets the constraint. 0.4 ns is the value obtained by forgetting to subtract the setup time, and 0.5 ns by adding the setup time instead. A negative slack means a violation.

A path has a clock period of 1.0 ns, a clock-to-output delay of 0.1 ns, a combinational logic delay of 0.85 ns and a setup time of 0.08 ns. If the clock arrives at the capturing flip-flop 0.05 ns later than at the launching flip-flop, what is the setup slack?

  1. A−0.03 ns
  2. B+0.02 ns
  3. C−0.08 ns
Show answer and explanation

Answer: B. +0.02 ns

When the capture clock arrives late (positive skew), the capturing edge shifts later, giving more time for setup. The required time is 1.0 + 0.05 − 0.08 = 0.97 ns and the arrival time is 0.1 + 0.85 = 0.95 ns, so the slack is +0.02 ns. −0.03 ns ignores the skew, and −0.08 ns treats the skew in the opposite direction (as if the capture clock arrived early). Note that the same skew works against hold.

Slack in the explanations

Questions that mention Slack (10)

  1. In a synchronous circuit with a clock period of 2.0 ns, the launching flip-flop's clock-to-output delay is 0.2 ns, the combinational logic delay is 1.4 ns and the capturing flip-flop's setup time is 0.1 ns. With zero clock skew, what is the setup slack?
  2. A path has a clock period of 1.0 ns, a clock-to-output delay of 0.1 ns, a combinational logic delay of 0.85 ns and a setup time of 0.08 ns. If the clock arrives at the capturing flip-flop 0.05 ns later than at the launching flip-flop, what is the setup slack?
  3. The launching flip-flop's minimum clock-to-output delay is 0.08 ns, the minimum combinational logic delay is 0.02 ns and the capturing flip-flop's hold time is 0.05 ns. If the clock arrives at the capturing flip-flop 0.1 ns later than at the launching flip-flop, what is the hold slack?
  4. A hold violation (slack −0.03 ns) is found on an ordinary path that launches and captures on the rising edge of the same clock. How is this violation affected if the clock frequency is halved?
  5. On a path with a clock period of 1.25 ns (800 MHz), the clock-to-output delay plus combinational logic delay totals 1.05 ns, the setup time is 0.05 ns, and the setup clock uncertainty is set to 0.05 ns. What is the setup slack?
  6. For OCV derating in setup analysis, the launch clock path and data path delays are multiplied by 1.1 and the capture clock path delay by 0.9. With a launch clock path of 1.0 ns, a data path (including clock-to-output) of 1.5 ns, a capture clock path of 1.0 ns (no common portion), a period of 3.0 ns and a setup time of 0.1 ns, what is the setup slack?
  7. In a circuit running on a 2.0 ns clock, a path has a data arrival time (clock-to-output plus combinational logic delay) of 3.3 ns and a setup time of 0.1 ns. Since this path only needs to capture once every two cycles, a setup multicycle path of 2 is set. What is the setup slack?
  8. Which correctly describes WNS and TNS as they appear in STA reports?
  9. When the clock arrives at the capturing flip-flop later than at the launching flip-flop (positive skew), what is the effect on setup and hold?
  10. In STA with OCV derating, when the launch and capture clock paths share a common portion, which correctly describes CRPR (common path pessimism removal)?

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Related terms

Setup time Flip-flop OCV (on-chip variation) Derating STA (static timing analysis) Clock skew Hold time Clock uncertainty Jitter Place and route

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