What is Asynchronous FIFO?

A FIFO written and read on separate clocks, used to pass multi-bit data between clock domains. Its pointers are converted to Gray code before being synchronized into the other domain to decide full and empty. The pointers have one more bit than the address to distinguish wrap-around.

Japanese name: 非同期FIFO

Asynchronous FIFO appears in 10 practice questions across 1 topic, including Timing analysis and CDC.

Asynchronous FIFO structure Write side (wclk) Read side (rclk) Dual-port RAM R/W on two clocks Write data Write pointer To Gray code Read data Read pointer To Gray code 2-FF sync Empty check 2-FF sync Full check Gray-code pointer In Gray code, only 1 bit changes per increment
Asynchronous FIFO structure · View in diagrams

Field: Timing analysis and CDC

Try it: questions about Asynchronous FIFO

Why are the write and read pointers of an asynchronous FIFO converted to Gray code before being synchronized into the other domain?

  1. ABecause Gray code halves the number of bits, so fewer synchronizers are needed
  2. BBecause only one bit changes per increment, so even if captured mid-change the result is the correct value from before or after the increment
  3. CBecause Gray-coded signals do not go metastable, so synchronization becomes unnecessary
Show answer and explanation

Answer: B. Because only one bit changes per increment, so even if captured mid-change the result is the correct value from before or after the increment

A binary pointer can change multiple bits at once, as in 0111 to 1000, so synchronizing each bit separately can yield a completely unrelated value. With Gray code only one bit changes per increment, so even if that bit goes metastable and resolves to either the old or new value, the result is the value from before or after the increment. The receiver merely sees a slightly stale value, so the FIFO does not break. The number of bits does not change, and metastability itself can still occur, so synchronizers are still required.

In a 16-word-deep asynchronous FIFO, why are the write and read pointers made 5 bits, one bit more than the address?

  1. ABecause 5 bits are needed to represent the addresses of 16 words
  2. BSo that when the pointers match, empty (same lap) can be distinguished from full (one lap apart)
  3. CTo use the extra bit as parity for detecting pointer errors
Show answer and explanation

Answer: B. So that when the pointers match, empty (same lap) can be distinguished from full (one lap apart)

The addresses of 16 words fit in 4 bits, but with 4-bit pointers alone, when the read and write addresses match it is impossible to tell whether the FIFO is empty because everything has been read, or full because writing has gone a full lap and caught up. Adding a fifth bit that indicates the lap means that, comparing in binary, the FIFO is empty when all 5 bits match and full when only the MSB differs. With Gray code pointers, the comparison for full is slightly different. The bit is not used as parity.

Asynchronous FIFO in the explanations

Questions that mention Asynchronous FIFO (10)

  1. Why are the write and read pointers of an asynchronous FIFO converted to Gray code before being synchronized into the other domain?
  2. In a 16-word-deep asynchronous FIFO, why are the write and read pointers made 5 bits, one bit more than the address?
  3. In a 16-word-deep asynchronous FIFO with 5-bit Gray code pointers, what is the correct condition for detecting full on the write side?
  4. In an asynchronous FIFO, the other side's pointer is used after synchronization, so the pointer value seen is 2–3 cycles stale. What effect does this delay have on full/empty detection?
  5. In an asynchronous FIFO with a 100 MHz write side and an 80 MHz read side, the write side writes a 100-word burst at one word per cycle and the read side reads one word per cycle. There is ample idle time between bursts. What is the minimum depth needed to avoid overflow (ignore synchronization delay)?
  6. Why can it be a problem to leave the paths that carry an asynchronous FIFO's Gray code pointers to the other domain unconstrained (false path) just because they are asynchronous?
  7. Each bit of 4-bit data is passed to another clock domain through its own two-stage synchronizer. What problem can occur when the data changes from 0111 to 1000?
  8. Which is a correct way to pass multi-bit data safely to another clock domain?
  9. What constraint applies when passing pulses from a fast clock domain to a slow one with toggle synchronization?
  10. Which is a drawback of transferring data between clock domains with a handshake?

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Related terms

Gray code Clock domain Handshake Metastability Synchronizer Yield False path Place and route Clock uncertainty Critical path

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