Advanced transistors (FinFET and GAA)

Check the key points of advanced transistors — FinFET and GAA structures, short-channel effects, high-k/metal gates and strain engineering — with multiple-choice questions.

—Your accuracy
0 / 50Questions answered
Practice this topicAll questions in this topic, in random order Weak questionsRetry only the questions you last got wrong

Advanced transistors (FinFET and GAA): key points

As transistors shrink, short-channel effects make it harder for the gate to control the channel. FinFETs, whose fin-shaped channel is surrounded by the gate on three sides, solved this, and the design has evolved further into gate-all-around (GAA) transistors that surround the channel completely.

High-k/metal gates, which suppress gate leakage, and strain techniques, which raise mobility, are also important technologies behind advanced transistors.

All Advanced transistors (FinFET and GAA) questions (50)

  1. Which correctly describes the structure of a FinFET?
  2. Which correctly describes a GAA (gate-all-around) transistor?
  3. Which describes a short-channel effect in MOSFETs?
  4. What is the main reason for using high-k (high-dielectric-constant) materials for the gate insulator?
  5. What is the main purpose of applying strain (stress) to a transistor's channel?
  6. Which correctly describes EOT (equivalent oxide thickness)?
  7. Which correctly describes the SOI (silicon on insulator) structure?
  8. Which correctly describes DIBL (drain-induced barrier lowering)?
  9. How is the effective channel width of a FinFET adjusted?
  10. Which correctly describes the CFET (complementary FET), researched as the structure to follow GAA?
  11. In high-k/metal gate transistors, which is one of the main ways to adjust the threshold voltage?
  12. Which correctly describes the gate-last (replacement metal gate) process?
  13. What is an advantage of fully depleted SOI (FD-SOI) transistors?
  14. In very small transistors, what is the phenomenon called in which the threshold voltage varies because of statistical variation in the number and positions of dopant atoms in the channel?
  15. Compared with FinFETs, what is a design advantage of nanosheet GAA transistors?
  16. Which technique, used to make the thin fins of FinFETs, uses sidewall spacers to create patterns finer than the lithography limit?
  17. In manufacturing nanosheet GAA transistors, why is only the SiGe selectively removed from stacked alternating Si and SiGe layers?
  18. What is the cause of self-heating, which tends to be a problem in FinFETs and SOI transistors?
  19. In highly scaled transistors, which factors are becoming increasingly important limits on performance?
  20. Which correctly describes materials such as molybdenum disulfide (MoS2), researched as channel materials for future ultra-small transistors?
  21. What is the main purpose of growing raised crystal on the fins in the source and drain of a FinFET by epitaxial growth?
  22. What is the basic way to reduce metal-semiconductor contact resistance?
  23. Which is considered to show the real degree of logic scaling better than the process generation (node) name?
  24. Which devices are being researched with the aim of breaking the 60 mV/dec subthreshold swing barrier?
  25. In nanosheet GAA, what is the main role of the insulator (inner spacer) placed between the gate and the source/drain between the sheets?
  26. When standard cell height is expressed in the number of routing tracks, what is the effect of reducing the number of tracks?
  27. What is the purpose of using several types of transistors with different threshold voltages on the same chip?
  28. Which technique covers the gate with insulator so that a slightly misaligned contact does not short to the gate?
  29. Why are SiGe and germanium considered or adopted instead of silicon as pMOS channel materials?
  30. Which 3D integration method builds transistor layers one after another on the wafer, without bonding chips?
  31. Which company and generation first put FinFETs (called Tri-Gate by Intel) into volume-production logic products?
  32. Which company and generation were first to announce volume production of GAA (nanosheet) transistors?
  33. What is the main purpose of scaling transistors down?
  34. What does "nanosheet" refer to in a nanosheet GAA transistor?
  35. What does the "k" in "high-k gate dielectric" represent?
  36. For a FinFET whose fin is 50 nm tall and 6 nm wide, which is closest to the effective channel width per fin (the perimeter wrapped by the gate)?
  37. To adequately suppress short-channel effects in a FinFET, what is generally required of the fin width?
  38. In high-k/metal gate transistors, why is a very thin layer such as SiO2 often placed between the silicon and the high-k film (such as hafnium oxide)?
  39. Why have III-V compound semiconductors such as InGaAs been researched as future nMOS channel materials?
  40. Which correctly describes the transistor performance metric "Ion/Ioff ratio"?
  41. How did the subthreshold swing (SS) generally change with the move from planar transistors to FinFETs?
  42. As physical scaling becomes harder, what is the practice of considering design and process technology together to optimize area and performance called?
  43. In nanosheet GAA transistors now in production, how many nanosheets are typically stacked in one transistor?
  44. Which structure places nMOS and pMOS nanosheets close together on either side of a thin insulating wall to reduce cell area?
  45. What is the state called in which the channel is so short that carriers travel from source to drain almost without scattering?
  46. Which transistor has a source, channel and drain of the same conductivity type and doping, with no PN junctions?
  47. In FinFETs built on bulk substrates, what is the purpose of a heavily doped layer at the base of the fin (the part the gate controls poorly)?
  48. Which correctly describes the "scale length (natural length) λ" used to estimate the severity of short-channel effects?
  49. What is an effect of quantum confinement when fins or nanosheets are thinned to a few nanometers?
  50. In a FinFET made in the usual orientation on a (100) wafer, the fin sidewalls that form the channel are mainly (110) planes. What is the effect on mobility?

Other topics in Devices